2X2 800 Mbps LVDS Crosspoint Switch# DS90CP22MX8 Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS90CP22MX8 from National Semiconductor (NSC) is a high-performance 21-bit Channel Link II deserializer designed for high-speed digital video and data transmission applications. Typical use cases include:
Digital Display Interfaces
- LCD panel timing controller (T-CON) interfaces
- Digital signage and large format displays
- Medical imaging displays requiring high-resolution video
- Automotive infotainment systems and digital clusters
High-Speed Data Links
- Industrial camera interfaces
- Machine vision systems
- Broadcast video equipment
- Test and measurement instrumentation
Embedded Systems
- Board-to-board communication in compact systems
- Backplane interconnects in telecommunications equipment
- Digital signal processor interfaces
### Industry Applications
Consumer Electronics
- High-definition televisions and monitors
- Gaming consoles and VR/AR systems
- Professional video editing workstations
Automotive
- Advanced driver assistance systems (ADAS)
- Center stack displays and digital instrument clusters
- Rear-seat entertainment systems
Medical
- Surgical display systems
- Diagnostic imaging equipment
- Patient monitoring displays
Industrial
- Factory automation HMI displays
- Process control visualization systems
- Robotics control interfaces
### Practical Advantages and Limitations
Advantages:
- High Bandwidth : Supports up to 2.38 Gbps total bandwidth with 21-bit parallel output
- Low Power : Typically consumes 120mW at 3.3V supply
- Robust Performance : Built-in pre-emphasis and equalization for signal integrity
- Compact Solution : Reduces cable count and connector size compared to parallel interfaces
- EMI Reduction : LVDS technology minimizes electromagnetic interference
Limitations:
- Fixed Configuration : Limited to specific 21-bit deserialization architecture
- Distance Constraints : Maximum reliable distance typically 5-10 meters depending on cable quality
- Clock Recovery Dependency : Requires stable reference clock for proper operation
- Temperature Range : Commercial temperature range may not suit extreme environments without additional measures
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Decoupling
- Pitfall : Inadequate decoupling causing signal integrity issues and increased jitter
- Solution : Use multiple 0.1μF ceramic capacitors placed close to power pins, with bulk capacitance (10μF) for stability
Clock Management
- Pitfall : Unstable reference clock leading to synchronization failures
- Solution : Implement high-quality crystal oscillator with proper termination and keep clock traces short and impedance-controlled
Signal Integrity
- Pitfall : Excessive jitter due to improper cable selection or termination
- Solution : Use controlled impedance cables (100Ω differential), implement proper termination resistors, and consider signal conditioning
### Compatibility Issues
With Serializers
- Must be paired with compatible Channel Link II serializers (e.g., DS90CP21)
- Ensure matching data rates and clocking schemes between transmitter and receiver
With Microcontrollers/FPGAs
- Verify voltage level compatibility (3.3V LVCMOS/LVTTL)
- Check timing requirements for parallel interface setup/hold times
- Ensure proper power sequencing to prevent latch-up
Power Supply Requirements
- Requires clean 3.3V supply with proper sequencing
- May need separate analog and digital power domains in noise-sensitive applications
### PCB Layout Recommendations
Differential Pair Routing
- Maintain consistent 100Ω differential impedance for serial inputs
- Keep differential pairs closely coupled with minimal length mismatch (<10 mils)
- Route away from noisy digital signals and power supplies
Power Distribution
- Use separate power planes for analog and digital sections
- Implement star-point grounding for sensitive analog circuits
- Ensure low-im
