2X2 800 Mbps LVDS Crosspoint Switch# DS90CP22M8 Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS90CP22M8 is a high-performance 21-bit Channel Link II deserializer designed for converting serialized data back to parallel CMOS/TTL levels. This component is particularly valuable in applications requiring high-speed data transmission over limited cable interfaces.
Primary Use Cases:
- Digital Display Interfaces : Converts serialized video data from FPD-Link transmitters to parallel RGB data for LCD/OLED panels
- Camera Systems : Processes high-speed serial video streams in automotive and industrial camera applications
- Data Acquisition Systems : Handles serial-to-parallel conversion in measurement and test equipment
- Embedded Vision : Interfaces between serial links and image processing units in machine vision systems
### Industry Applications
Automotive Industry:
- Infotainment display systems
- Rear-view and surround-view camera systems
- Advanced driver assistance systems (ADAS)
- Digital instrument clusters
Consumer Electronics:
- High-resolution display panels
- Digital signage systems
- Professional video equipment
- Gaming displays
Industrial Applications:
- Industrial machine vision cameras
- Medical imaging displays
- Test and measurement equipment
- Robotics vision systems
### Practical Advantages and Limitations
Advantages:
- High-Speed Operation : Supports data rates up to 2.38 Gbps, enabling high-resolution video transmission
- Noise Immunity : LVDS technology provides excellent noise rejection in electrically noisy environments
- Cable Reduction : Single twisted-pair cable replaces multiple parallel data lines, reducing system cost and complexity
- Low Power Consumption : Typically operates at 120mW, suitable for power-constrained applications
- Integrated Features : Includes built-in termination resistors and PLL circuitry
Limitations:
- Fixed Configuration : Limited to specific data mapping configurations
- Distance Constraints : Maximum cable length typically 5-10 meters depending on data rate and cable quality
- Clock Requirements : Requires precise clock synchronization with paired serializer
- Power Sequencing : Sensitive to improper power-up sequences
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Issues:
- Pitfall : Inadequate power supply decoupling causing signal integrity problems
- Solution : Implement proper decoupling capacitors (0.1μF ceramic close to each power pin) and bulk capacitance (10μF) near the device
Signal Integrity Problems:
- Pitfall : Excessive jitter due to improper termination or impedance mismatch
- Solution : Ensure 100Ω differential termination on LVDS inputs and maintain controlled impedance throughout the signal path
Clock Synchronization:
- Pitfall : Clock skew between serializer and deserializer causing data corruption
- Solution : Use matched-length routing for clock and data pairs, implement proper clock recovery circuitry
### Compatibility Issues with Other Components
Serializer Pairing:
- Must be paired with compatible Channel Link II serializers (e.g., DS90CF22/23/24 family)
- Verify compatible data mapping and control signal configurations
Voltage Level Compatibility:
- LVDS inputs require 100Ω differential termination
- CMOS/TTL outputs compatible with 3.3V logic families
- Ensure proper level shifting when interfacing with 1.8V or 5V systems
Timing Constraints:
- Maximum data rate compatibility with connected processors or FPGAs
- Setup and hold time requirements for output data signals
### PCB Layout Recommendations
Power Distribution:
- Use separate power planes for analog and digital supplies
- Implement star-point grounding for noise-sensitive circuits
- Place decoupling capacitors within 2mm of power pins
Signal Routing:
- LVDS Pairs : Route as differential pairs with 100Ω differential impedance
- Length Matching
