800 Mbps 2x2 LVDS Crosspoint Switch 16-SOIC -40 to 85# DS90CP22M8NOPB Technical Documentation
*Manufacturer: NSC (National Semiconductor)*
## 1. Application Scenarios
### Typical Use Cases
The DS90CP22M8NOPB is a high-speed LVDS (Low-Voltage Differential Signaling) deserializer designed for converting serial LVDS data streams back into parallel CMOS/TTL outputs. Typical applications include:
- High-Speed Data Recovery : Converting 21-bit serialized data streams back to parallel 21-bit CMOS/TTL data with embedded clock recovery
- Display Interface Systems : Receiving video data from LVDS serializers in flat panel displays, digital signage, and automotive infotainment systems
- Backplane Communications : Data transmission across backplanes in telecommunications and networking equipment
- Camera Interfaces : High-speed image data transmission in industrial vision systems and medical imaging equipment
### Industry Applications
- Automotive Electronics : Instrument clusters, center stack displays, and rear-seat entertainment systems requiring robust EMI performance
- Industrial Automation : Machine vision systems, HMI panels, and control system displays operating in noisy environments
- Medical Imaging : Diagnostic display systems requiring high data integrity and reliable signal transmission
- Consumer Electronics : High-resolution displays in smart TVs, monitors, and digital advertising displays
- Telecommunications : Base station equipment and network switching systems requiring reliable high-speed data links
### Practical Advantages and Limitations
Advantages:
- EMI Reduction : LVDS technology significantly reduces electromagnetic interference compared to single-ended signaling
- Power Efficiency : Low power consumption (typically 100mW at 3.3V supply)
- Noise Immunity : Excellent common-mode noise rejection up to ±1V
- Long Distance Capability : Supports cable lengths up to 10 meters with proper cabling
- Integrated Clock Recovery : Eliminates need for separate clock transmission lines
Limitations:
- Fixed Configuration : Supports specific data formats (21:7 deserialization ratio) without programmability
- Frequency Range : Limited to 35-85 MHz input clock frequency range
- Power Supply Sensitivity : Requires clean 3.3V power supply with proper decoupling
- Channel Matching : Requires careful PCB layout for differential pair routing
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Pitfall 1: Improper Termination
- Issue : Unterminated or incorrectly terminated LVDS lines causing signal reflections
- Solution : Implement 100Ω differential termination resistors close to receiver inputs
Pitfall 2: Power Supply Noise
- Issue : Switching noise coupling into analog PLL circuits
- Solution : Use separate power planes and extensive decoupling (0.1μF and 10μF capacitors)
Pitfall 3: Signal Integrity Degradation
- Issue : Long, unmatched trace lengths causing timing skew
- Solution : Maintain tight differential pair coupling and equal trace lengths (±5mm)
### Compatibility Issues with Other Components
LVDS Driver Compatibility:
- Compatible with DS90CP21 and similar 21-bit LVDS serializers
- Requires matching data format and clocking scheme
- Verify voltage level compatibility with other LVDS transmitters
Power Supply Considerations:
- 3.3V operation must match system power architecture
- May require level shifters when interfacing with 1.8V or 5V components
- Ensure proper sequencing with other system components
### PCB Layout Recommendations
Differential Pair Routing:
- Maintain consistent 100Ω differential impedance throughout the route
- Keep differential pairs tightly coupled with minimal spacing variations
- Route pairs on same layer without vias when possible
Power Distribution:
- Use star-point grounding for analog and digital sections
- Implement separate analog and digital ground planes connected at single point
- Place
