+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA# DS90CF388VJDX Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS90CF388VJDX from National Semiconductor (NS) is a 28-bit Channel Link II LVDS serializer primarily designed for high-speed digital video transmission. Typical applications include:
- Flat Panel Display Interfaces : Converts 28-bit parallel RGB data to serial LVDS streams for LCD monitors, industrial displays, and medical imaging displays
- Digital Signage Systems : Enables long-distance transmission between video sources and display panels in commercial advertising displays
- Automotive Infotainment : Connects head units to center stack displays in vehicle entertainment systems
- Medical Imaging Equipment : Transfers high-resolution video data from imaging processors to diagnostic displays
- Industrial Control Systems : Interfaces between control processors and operator panel displays in factory automation environments
### Industry Applications
Consumer Electronics :
- High-definition televisions and computer monitors
- Gaming console display interfaces
- Home theater projection systems
Professional/Industrial :
- Aviation and marine navigation displays
- Military command and control systems
- Test and measurement equipment displays
Medical :
- Ultrasound and MRI display subsystems
- Patient monitoring system displays
- Surgical imaging equipment
### Practical Advantages and Limitations
Advantages :
- High-Speed Operation : Supports pixel clock rates up to 85 MHz, enabling resolutions up to UXGA (1600×1200)
- Noise Immunity : LVDS signaling provides excellent common-mode noise rejection
- Cable Reduction : Converts 28 parallel signals to 4 differential pairs, reducing cable size and cost
- Low Power Consumption : Typically 200 mW at 3.3V supply
- Integrated Termination : On-chip termination resistors simplify board design
Limitations :
- Fixed Configuration : Limited to specific pixel formats (24-bit RGB + control signals)
- Distance Constraints : Maximum reliable transmission distance of approximately 10 meters
- Clock Synchronization : Requires careful clock distribution and synchronization
- Power Sequencing : Sensitive to improper power-up sequences
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Issues :
- Pitfall : Inadequate decoupling causing signal integrity problems
- Solution : Use 0.1 μF ceramic capacitors placed within 5 mm of each power pin, plus bulk 10 μF tantalum capacitors
Signal Integrity Problems :
- Pitfall : Excessive jitter due to improper PCB layout
- Solution : Maintain controlled impedance (100Ω differential) for LVDS pairs and minimize trace length mismatches (< 5 mm)
ESD Damage :
- Pitfall : LVDS I/O susceptibility to electrostatic discharge
- Solution : Implement TVS diodes on all LVDS outputs and follow proper ESD handling procedures
### Compatibility Issues with Other Components
LVDS Receiver Compatibility :
- Must pair with compatible LVDS deserializers (DS90CF389)
- Verify compatible data mapping and control signal protocols
Power Supply Sequencing :
- Core (3.3V) and I/O voltages must ramp up simultaneously
- Incompatible with systems having staggered power sequencing
Clock Domain Crossing :
- Requires clean, low-jitter pixel clock source
- May need clock cleaning PLL when interfacing with noisy clock sources
### PCB Layout Recommendations
General Layout Guidelines :
- Place serializer close to video source to minimize parallel bus length
- Use 4-layer PCB minimum (signal, ground, power, signal)
- Maintain continuous ground plane beneath LVDS traces
LVDS Pair Routing :
- Route differential pairs as closely coupled microstrip lines
- Maintain consistent spacing (typically 0.15 mm) between pair members
- Keep pair-to-pair spacing ≥ 3× trace width to
