Dual Pixel LVDS Display Interface / FPD-Link Transmitter# DS90C387AVJD Technical Documentation
*Manufacturer: National Semiconductor (NS)*
## 1. Application Scenarios
### Typical Use Cases
The DS90C387AVJD is a high-performance LVDS (Low-Voltage Differential Signaling) serializer designed for high-speed digital video transmission applications. Typical use cases include:
- Digital Display Interfaces : Primary application in LCD/OLED display systems for transmitting RGB data from timing controllers to display panels
- Medical Imaging Displays : Used in high-resolution medical monitors requiring precise color reproduction and low EMI
- Automotive Infotainment Systems : Integrated into center console displays and digital instrument clusters
- Industrial Control Panels : Deployed in manufacturing equipment interfaces and process control displays
- Avionics Displays : Suitable for aircraft cockpit displays requiring robust signal integrity
### Industry Applications
Consumer Electronics
- High-definition televisions and monitors
- Digital signage and advertising displays
- Gaming consoles and VR headset displays
Professional/Industrial
- Broadcast studio monitors
- Digital cinema projection systems
- Industrial HMI (Human-Machine Interface) panels
Transportation
- Automotive center information displays
- Aerospace cockpit instrumentation
- Marine navigation systems
### Practical Advantages
Strengths:
- High-Speed Operation : Supports pixel clocks up to 85 MHz, enabling WUXGA (1920×1200) resolution
- EMI Reduction : LVDS technology significantly reduces electromagnetic interference compared to parallel interfaces
- Power Efficiency : Low power consumption (typical 150mW at 3.3V supply)
- Noise Immunity : Differential signaling provides excellent common-mode noise rejection
- Cable Reduction : Serializes 28 parallel signals into 4 LVDS pairs, reducing cable size and cost
Limitations:
- Distance Constraints : Maximum recommended cable length of 10 meters
- Clock Recovery Dependency : Requires precise clock recovery at receiver end
- Component Matching : Must be paired with compatible LVDS deserializer (typically DS90CF388)
- Power Sequencing : Sensitive to improper power-up sequences
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Pitfall 1: Improper Termination
- Issue : Reflections and signal integrity problems due to mismatched impedance
- Solution : Implement 100Ω differential termination resistors at receiver inputs, placed close to connector
Pitfall 2: Power Supply Noise
- Issue : Switching noise coupling into analog sections
- Solution : Use separate LDO regulators for analog and digital supplies with proper decoupling
Pitfall 3: Clock Jitter
- Issue : Excessive jitter causing display artifacts
- Solution : Ensure clean clock source with proper bypassing and minimal trace length
Pitfall 4: ESD Vulnerability
- Issue : LVDS lines susceptible to electrostatic discharge
- Solution : Incorporate TVS diodes on all LVDS pairs and follow proper ESD handling procedures
### Compatibility Issues
Component Interoperability
- Recommended Pairing : DS90CF388 deserializer for complete channel solution
- FPGA Interfaces : Compatible with LVDS-capable FPGAs (Xilinx, Altera) with proper termination
- Microcontroller Limitations : May require level translation when interfacing with 1.8V or 2.5V MCUs
Signal Level Compatibility
- Inputs: TTL/CMOS compatible (0-3.3V)
- Outputs: LVDS levels (typical 350mV swing)
- Not directly compatible with RS-422, PECL, or CML interfaces without translation
### PCB Layout Recommendations
Power Distribution
- Use separate power planes for analog (PLLVCC) and digital (VCC) supplies
- Implement star-point grounding
