Dual Pixel LVDS Display Interface / FPD-Link Transmitter 100-TQFP -10 to 70# DS90C387AVJDNOPB LVDS Serializer Technical Documentation
Manufacturer : NSC (National Semiconductor)
## 1. Application Scenarios
### Typical Use Cases
The DS90C387AVJDNOPB is a 21-bit to 3-channel LVDS serializer primarily designed for high-speed digital video transmission applications. Key use cases include:
- Digital Display Interfaces : Transmits RGB data from graphics controllers to LCD panels in laptops, monitors, and industrial displays
- Automotive Infotainment Systems : Connects head units to rear-seat entertainment displays and center stack displays
- Medical Imaging Displays : Transmits high-resolution video data to medical monitors requiring low EMI
- Industrial Control Systems : Interfaces between control units and operator panels in factory automation environments
- Avionics Displays : Aircraft cockpit displays requiring robust signal integrity over longer cable runs
### Industry Applications
- Consumer Electronics : High-definition televisions, digital signage, gaming consoles
- Automotive : Center console displays, instrument clusters, heads-up displays
- Medical : Patient monitoring systems, surgical displays, diagnostic imaging equipment
- Industrial : Human-machine interfaces (HMI), process control displays, test and measurement equipment
- Telecommunications : Network equipment status displays, control panel interfaces
### Practical Advantages and Limitations
Advantages:
- EMI Reduction : LVDS technology significantly reduces electromagnetic interference compared to parallel interfaces
- Cable Reduction : 21-bit parallel data transmitted over only 3 differential pairs plus clock
- Long Distance Transmission : Capable of reliable data transmission up to 10 meters
- Low Power Consumption : Typically operates at 3.3V with power-down mode for energy efficiency
- High Speed Operation : Supports pixel clock rates up to 85 MHz, enabling high-resolution displays
Limitations:
- Fixed Configuration : Limited to specific 21-bit input format (6:6:6 RGB or similar)
- Clock Dependency : Requires precise clock synchronization between serializer and deserializer
- PCB Complexity : Requires controlled impedance routing and proper termination
- Compatibility : Must be paired with compatible LVDS deserializer (typically DS90CF388)
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Pitfall 1: Improper Termination
- Issue : Unterminated or incorrectly terminated LVDS lines cause signal reflections
- Solution : Implement 100Ω differential termination at the receiver end only
Pitfall 2: Ground Bounce
- Issue : Inadequate decoupling causes power supply noise
- Solution : Place 0.1μF decoupling capacitors within 5mm of power pins, with bulk capacitance nearby
Pitfall 3: Clock Skew
- Issue : Clock-to-data skew exceeding specifications causes timing violations
- Solution : Maintain matched trace lengths for all data channels relative to clock
Pitfall 4: ESD Damage
- Issue : LVDS I/Os susceptible to electrostatic discharge
- Solution : Implement ESD protection diodes on all LVDS outputs
### Compatibility Issues with Other Components
Deserializer Compatibility:
- Must pair with DS90CF388 or equivalent 3-channel LVDS deserializer
- Verify compatible data mapping formats between serializer and deserializer
Power Supply Sequencing:
- Ensure I/O voltages are applied before or simultaneously with core voltage
- Implement proper power sequencing to prevent latch-up
Clock Source Requirements:
- Requires stable, low-jitter clock source (typically 1-2% tolerance)
- Clock must meet LVCMOS/LVTTL input specifications
### PCB Layout Recommendations
Differential Pair Routing:
- Maintain consistent 100Ω differential impedance
- Keep trace lengths matched within ±5mm for all data
