Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA# DS90C387 Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS90C387 is a high-performance LVDS serializer primarily designed for high-speed digital video transmission applications. Typical implementations include:
- LCD Panel Interfaces : Converts 21-bit RGB data and 3 control signals to a single LVDS data stream
- Medical Imaging Displays : Used in high-resolution medical monitors requiring precise color reproduction
- Industrial HMI Systems : Interfaces between graphics controllers and industrial touchscreen displays
- Automotive Infotainment : Transmits video data from head units to center console displays
- Avionics Displays : Critical for cockpit displays requiring robust EMI performance
### Industry Applications
Medical Equipment :
- Ultrasound systems
- MRI/CT scanner displays
- Patient monitoring stations
*Advantage*: Excellent EMI characteristics prevent interference with sensitive medical equipment
Automotive Systems :
- Navigation displays
- Rear-seat entertainment
- Digital instrument clusters
*Advantage*: Robust operation across automotive temperature ranges (-40°C to +85°C)
Industrial Control :
- PLC operator interfaces
- Process control monitors
- Manufacturing equipment displays
*Advantage*: Reliable performance in electrically noisy environments
### Practical Advantages and Limitations
Advantages :
- Power Efficiency : Consumes only 300mW typical at 65MHz
- EMI Performance : LVDS signaling reduces electromagnetic interference by 20-30dB compared to CMOS
- Cable Reduction : Single cable solution replaces 24+ parallel lines
- Long Distance Capability : Supports cable lengths up to 10 meters
- Integrated DC Balancing : Reduces baseline wander in AC-coupled applications
Limitations :
- Fixed Data Format : Limited to 21-bit RGB + 3 control signal configuration
- Clock Speed Dependency : Maximum resolution limited by pixel clock frequency
- Power Sequencing : Requires careful power-up/down sequencing to prevent latch-up
- Component Matching : Requires compatible deserializer (DS90C388) for complete solution
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Issues :
- *Pitfall*: Inadequate decoupling causing signal integrity problems
- *Solution*: Implement 0.1μF ceramic capacitors within 5mm of each power pin
Clock Jitter :
- *Pitfall*: Excessive clock jitter from poor clock source selection
- *Solution*: Use crystal oscillators with <50ps period jitter
Impedance Mismatch :
- *Pitfall*: Improper termination causing signal reflections
- *Solution*: Implement 100Ω differential termination at receiver end
### Compatibility Issues
Graphics Controller Interface :
- Voltage Level Compatibility : 3.3V TTL/CMOS inputs require level shifting if controller operates at different voltages
- Timing Constraints : Pixel clock must meet setup/hold times specified in datasheet
- Control Signal Mapping : VSYNC, HSYNC, and DE signals must be properly mapped
Deserializer Pairing :
- Must be used with DS90C388 for complete channel
- Channel-to-channel skew compensation required for multi-link systems
- Power sequencing must be coordinated between serializer and deserializer
### PCB Layout Recommendations
Power Distribution :
```markdown
- Use separate power planes for analog and digital supplies
- Implement star-point grounding near device
- Place decoupling capacitors: 10μF bulk + 0.1μF ceramic per power pin
```
Signal Routing :
- LVDS Pairs : Maintain 100Ω differential impedance with 5% tolerance
- Pair Spacing : Keep at least 3x trace width between differential pairs
