+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz# DS90C385MTDX Technical Documentation
*Manufacturer: National Semiconductor (NS)*
## 1. Application Scenarios
### Typical Use Cases
The DS90C385MTDX is a high-speed LVDS (Low-Voltage Differential Signaling) serializer designed for converting 21 bits of CMOS/TTL data into three LVDS data streams. Primary applications include:
- Flat Panel Display Interfaces : Driving LCD panels in automotive infotainment systems, medical displays, and industrial monitors
- Digital Video Transmission : High-speed video data transmission in surveillance systems and digital signage
- Embedded Display Systems : Integration into single-board computers and embedded systems requiring robust display connectivity
- Camera Systems : Transmission of high-resolution image data from sensors to processing units
### Industry Applications
- Automotive : Instrument clusters, center stack displays, and rear-seat entertainment systems
- Medical Imaging : Patient monitoring displays and diagnostic equipment interfaces
- Industrial Automation : HMI panels, control system displays, and process monitoring equipment
- Consumer Electronics : High-end gaming displays and professional video editing equipment
- Aerospace : Cockpit displays and avionics systems requiring EMI-resistant data transmission
### Practical Advantages and Limitations
Advantages:
- EMI Performance : LVDS technology provides excellent electromagnetic compatibility with reduced radiation
- Power Efficiency : Operates at 3.3V with typical power consumption of 120mW
- Noise Immunity : Differential signaling ensures reliable data transmission in noisy environments
- High Speed : Supports pixel clocks up to 85MHz, enabling high-resolution display support
- Cable Reduction : Minimizes interconnect complexity through serialization
Limitations:
- Distance Constraints : Optimal performance limited to approximately 10 meters without repeaters
- Clock Synchronization : Requires precise clock management for reliable data recovery
- Component Matching : Requires complementary deserializer (DS90C386) for complete system implementation
- Power Sequencing : Sensitive to improper power-up sequences which may cause latch-up
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Pitfall 1: Improper Termination
- Issue : Unterminated or incorrectly terminated transmission lines cause signal reflections
- Solution : Implement 100Ω differential termination at the receiver end, placed as close as possible to the deserializer inputs
Pitfall 2: Power Supply Noise
- Issue : Switching noise from digital circuits contaminates analog power supplies
- Solution : Use separate power planes for analog and digital sections with proper decoupling (0.1μF ceramic capacitors placed within 5mm of power pins)
Pitfall 3: Clock Jitter
- Issue : Excessive clock jitter degrades timing margins
- Solution : Implement clean clock distribution with proper buffering and use low-jitter clock sources
Pitfall 4: ESD Vulnerability
- Issue : LVDS lines are susceptible to electrostatic discharge
- Solution : Incorporate TVS diodes on all differential pairs and follow proper ESD handling procedures
### Compatibility Issues
Component Compatibility:
- Requires matching deserializer DS90C386 for complete channel implementation
- Compatible with standard LVDS receivers but optimized for paired operation
- May require level shifting when interfacing with 5V CMOS devices
Signal Integrity Considerations:
- Maintain 100Ω differential impedance throughout the transmission path
- Avoid mixing with single-ended signals in same cable harness
- Ensure common-mode voltage compatibility with receiving devices
### PCB Layout Recommendations
Differential Pair Routing:
- Maintain consistent differential impedance of 100Ω ±10%
- Keep trace lengths matched within 5mm to minimize skew
- Route differential pairs as symmetrical microstrip or stripline configurations
- Maintain minimum 3X trace width spacing to other signals
Power Distribution:
