+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link# DS90C363BMT Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS90C363BMT is a high-performance LVDS (Low-Voltage Differential Signaling) serializer designed for high-speed digital video transmission applications. This component is particularly optimized for converting 21 bits of CMOS/TTL data into three LVDS data streams plus a dedicated LVDS clock channel.
Primary applications include:
- Flat Panel Display Interfaces : Driving LCD panels in automotive infotainment systems, medical monitors, and industrial HMI displays
- Digital Video Distribution : Transmitting RGB video signals from graphics controllers to display modules over extended distances
- Embedded Vision Systems : Camera interfaces and machine vision applications requiring robust signal transmission
- Portable Electronics : Tablet displays and high-resolution mobile device screens
### Industry Applications
Automotive Industry:
- Center Stack Displays : Instrument clusters and infotainment screens
- Rear-Seat Entertainment : Video distribution to multiple displays
- Advanced Driver Assistance Systems (ADAS) : Camera display interfaces
- Operating Conditions : -40°C to +85°C temperature range suits automotive requirements
Medical Equipment:
- Patient monitoring displays
- Diagnostic imaging consoles
- Surgical display systems
- Advantage : EMI reduction critical for sensitive medical electronics
Industrial Automation:
- Human-Machine Interface (HMI) panels
- Process control displays
- Factory automation monitoring screens
- Benefit : Noise immunity in electrically noisy environments
### Practical Advantages and Limitations
Advantages:
- EMI Reduction : LVDS technology significantly reduces electromagnetic interference compared to parallel CMOS interfaces
- Cable Reduction : Transmits 21 data bits plus clock over only 4 differential pairs, reducing cable size and cost
- Long Distance Transmission : Capable of reliable transmission up to 10 meters with proper cabling
- Power Efficiency : Low power consumption (typically 75mW at 3.3V supply)
- High Speed : Supports pixel clocks up to 85MHz, enabling resolutions up to UXGA (1600×1200)
Limitations:
- Fixed Configuration : Limited to specific 21-bit RGB formats (6 bits per color plus control signals)
- Point-to-Point Only : Designed for single-source to single-destination applications
- Clock Dependency : Requires precise clock synchronization between transmitter and receiver
- Power Sequencing : Sensitive to improper power-up sequences
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Issues:
- Pitfall : Inadequate decoupling causing signal integrity problems
- Solution : Implement 0.1μF ceramic capacitors placed within 5mm of each power pin, plus bulk 10μF tantalum capacitors
Signal Integrity Problems:
- Pitfall : Improper termination leading to signal reflections
- Solution : Use 100Ω differential termination resistors at the receiver end, matched to within 1% tolerance
Clock Jitter:
- Pitfall : Excessive clock jitter causing display artifacts
- Solution : Ensure clean power to clock circuitry and use high-quality crystal oscillators
### Compatibility Issues with Other Components
LVDS Receiver Compatibility:
- Must pair with compatible LVDS receivers like DS90CF364MT
- Critical Parameter Matching : Ensure receiver supports same data mapping and clock rates
Microcontroller/GPU Interfaces:
- Verify voltage level compatibility (3.3V CMOS/TTL)
- Check timing requirements match source device capabilities
- Timing Consideration : Setup and hold times must meet DS90C363BMT specifications
Power Management ICs:
- Requires clean 3.3V supply with minimal noise
- Power sequencing must follow manufacturer recommendations
### PCB Layout Recommendations
