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CY7C1372C-167AC from CYPRESS

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CY7C1372C-167AC

Manufacturer: CYPRESS

512K x 36/1M x 18 Pipelined SRAM with NoBL(TM)Architecture

Partnumber Manufacturer Quantity Availability
CY7C1372C-167AC,CY7C1372C167AC CYPRESS 54 In Stock

Description and Introduction

512K x 36/1M x 18 Pipelined SRAM with NoBL(TM)Architecture The CY7C1372C-167AC is a high-speed synchronous pipelined burst SRAM manufactured by Cypress Semiconductor. Here are its key specifications:

- **Type**: Synchronous Pipelined Burst SRAM
- **Density**: 4 Mbit (256K x 18)
- **Speed**: 167 MHz (6 ns access time)
- **Voltage**: 3.3V ±10%
- **Organization**: 256K words × 18 bits
- **Package**: 100-pin TQFP (Thin Quad Flat Pack)
- **Operating Temperature**: Commercial (0°C to +70°C)
- **I/O Type**: Common I/O (input/output shared)
- **Burst Modes**: Linear or Interleaved burst sequence
- **Features**: 
  - Byte Write capability (BW1, BW2, BW3, BW4)
  - ZZ (Sleep Mode) for power saving
  - JTAG Boundary Scan (IEEE 1149.1 compliant)
  - Single-cycle deselect for reduced power consumption
  - Clock-controlled, registered inputs for pipelined operation

This SRAM is designed for high-performance networking, telecommunications, and computing applications requiring fast access times and low power consumption.

Partnumber Manufacturer Quantity Availability
CY7C1372C-167AC,CY7C1372C167AC CY 20 In Stock

Description and Introduction

512K x 36/1M x 18 Pipelined SRAM with NoBL(TM)Architecture The CY7C1372C-167AC is a high-performance synchronous pipelined burst SRAM manufactured by Cypress Semiconductor. Here are the key specifications:

- **Organization**: 4Mbit (256K x 18)
- **Speed**: 167 MHz (6 ns access time)
- **Voltage Supply**: 3.3V (VDD) with 2.5V I/O (VDDQ)
- **Package**: 100-pin TQFP (Thin Quad Flat Pack)
- **Interface**: Synchronous with ZBT (Zero Bus Turnaround) feature
- **Burst Modes**: Linear or interleaved burst sequences
- **Operating Temperature**: Commercial (0°C to +70°C) or Industrial (-40°C to +85°C)
- **Features**: 
  - Byte Write capability
  - Single-cycle deselect
  - Self-timed write cycle
  - JTAG boundary scan (IEEE 1149.1 compliant)
  - Power-down mode for reduced standby current

This device is designed for high-speed networking, telecommunications, and cache memory applications.

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