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CY7C1370D-167AXI from CY,Cypress

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15.625ms

CY7C1370D-167AXI

Manufacturer: CY

18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture

Partnumber Manufacturer Quantity Availability
CY7C1370D-167AXI,CY7C1370D167AXI CY 65 In Stock

Description and Introduction

18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture The CY7C1370D-167AXI is a high-speed synchronous pipelined SRAM manufactured by Cypress Semiconductor (now Infineon Technologies). Here are the key specifications:

1. **Memory Size**: 4 Mbit (256K x 18-bit organization)  
2. **Speed**: 167 MHz operation  
3. **Voltage Supply**: 3.3V (VDD)  
4. **I/O Voltage**: 2.5V or 3.3V (VDDQ)  
5. **Access Time**: 3.0 ns (clock-to-data)  
6. **Architecture**: Synchronous pipeline with burst capability  
7. **Burst Modes**: Linear or interleaved burst sequences  
8. **Package**: 100-ball TQFP (Thin Quad Flat Pack)  
9. **Operating Temperature**: Industrial (-40°C to +85°C)  
10. **Features**:  
   - Single-cycle deselect  
   - ZZ sleep mode for power savings  
   - JTAG boundary scan support  

This SRAM is designed for high-performance networking, telecommunications, and computing applications.  

(Source: Cypress Semiconductor datasheet for CY7C1370D-167AXI)

Partnumber Manufacturer Quantity Availability
CY7C1370D-167AXI,CY7C1370D167AXI CYPRESS 280 In Stock

Description and Introduction

18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture The CY7C1370D-167AXI is a synchronous pipelined burst SRAM manufactured by Cypress Semiconductor. Here are its key specifications:

- **Type**: Synchronous Pipelined Burst SRAM
- **Density**: 4 Mbit (organized as 256K x 16)
- **Speed**: 167 MHz (6 ns access time)
- **Voltage Supply**: 3.3V (VDD = 3.3V ± 0.3V)
- **I/O Voltage**: 3.3V (VDDQ = 3.3V ± 0.3V)
- **Package**: 100-ball TQFP (Thin Quad Flat Pack)
- **Operating Temperature**: Industrial (-40°C to +85°C)
- **Burst Modes**: Linear or Interleaved (configurable)
- **Interface**: Synchronous (clock-controlled)
- **Features**: 
  - Byte Write Enable (BW) control
  - ZZ (Sleep Mode) for power saving
  - JTAG Boundary Scan (IEEE 1149.1 compliant)
  - Single-cycle deselect for pipelined operation

This SRAM is designed for high-performance applications requiring fast data access and low power consumption.

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