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CY7C1325G-100AXC from CY,Cypress

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15.625ms

CY7C1325G-100AXC

Manufacturer: CY

4-Mbit (256K x 18) Flow-Through Sync SRAM

Partnumber Manufacturer Quantity Availability
CY7C1325G-100AXC,CY7C1325G100AXC CY 24 In Stock

Description and Introduction

4-Mbit (256K x 18) Flow-Through Sync SRAM The CY7C1325G-100AXC is a high-speed synchronous pipelined SRAM manufactured by Cypress Semiconductor (now part of Infineon Technologies). Here are its key specifications:

1. **Memory Type**: Synchronous Pipelined SRAM  
2. **Density**: 8 Mbit (512K x 18)  
3. **Speed**: 100 MHz (10 ns access time)  
4. **Voltage Supply**: 3.3V ±10%  
5. **I/O Type**: LVTTL-compatible  
6. **Package**: 100-pin TQFP (Thin Quad Flat Pack)  
7. **Operating Temperature**: Commercial (0°C to +70°C)  
8. **Burst Modes**: Linear or Interleaved  
9. **Data Retention**: Supported in standby mode  
10. **Additional Features**:  
   - Byte Write Control  
   - Self-timed write cycle  
   - Single-cycle deselect  

This SRAM is commonly used in networking, telecommunications, and high-performance computing applications.

Partnumber Manufacturer Quantity Availability
CY7C1325G-100AXC,CY7C1325G100AXC CYPRESS 4 In Stock

Description and Introduction

4-Mbit (256K x 18) Flow-Through Sync SRAM The CY7C1325G-100AXC is a 3.3V 256K x 16 Synchronous Pipelined SRAM manufactured by Cypress Semiconductor. Here are its key specifications:

- **Density**: 4Mb (256K x 16)
- **Voltage Supply**: 3.3V ±10%
- **Speed**: 100MHz (10ns access time)
- **Organization**: 262,144 words × 16 bits
- **Package**: 100-pin TQFP (Thin Quad Flat Pack)
- **Operating Temperature**: Commercial (0°C to +70°C) or Industrial (-40°C to +85°C)
- **I/O Type**: Common I/O (separate input and output pins)
- **Features**: 
  - Synchronous pipeline operation
  - Single clock cycle deselect (except for burst operations)
  - Internally self-timed write cycle
  - Byte write control (Upper and Lower bytes)
  - Burst mode support (Linear or Interleaved)
  - JTAG boundary scan (IEEE 1149.1 compliant)
  - ZZ mode for power-down standby
  - Clock enable (CEN) input for power management

This SRAM is designed for high-performance applications requiring fast data access and low power consumption.

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