3-Pin Microprocessor Power Supply Supervisors# CAT803 Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The CAT803 is a microprocessor (μP) supervisory circuit designed to monitor power supplies in digital systems. Primary applications include:
Power-On Reset Generation
- Provides a reset pulse during power-up, power-down, and brown-out conditions
- Ensures proper microprocessor initialization when VCC rises above the reset threshold
- Typical reset timeout period: 140ms (minimum) to 1120ms (maximum)
Battery-Powered Systems
- Low quiescent current (typically 15μA) makes it ideal for portable devices
- Maintains system stability during battery voltage fluctuations
- Used in handheld medical devices, portable instrumentation, and consumer electronics
Industrial Control Systems
- Monitors 3V, 3.3V, and 5V power supplies in harsh environments
- Withstands industrial temperature ranges (-40°C to +85°C)
- Provides reliable system reset in motor control, PLCs, and automation equipment
### Industry Applications
- Consumer Electronics : Smart home devices, gaming consoles, set-top boxes
- Automotive : Infotainment systems, body control modules, telematics
- Medical : Patient monitoring equipment, portable diagnostic devices
- Industrial : Process control systems, robotics, power management
- Communications : Network equipment, base stations, routers
### Practical Advantages and Limitations
Advantages:
- High Accuracy : ±1.5% reset voltage threshold accuracy
- Low Power Consumption : 15μA typical supply current
- Small Package Options : SOT-23-5 and SC-70 packages save board space
- Manual Reset Capability : MR pin allows external reset triggering
- Wide Operating Range : 1.0V to 5.5V supply voltage range
Limitations:
- Fixed Timeout Period : Reset timeout is factory-set and cannot be adjusted
- Limited Voltage Options : Available in specific threshold voltages only
- No Watchdog Timer : Lacks additional monitoring features found in more complex supervisors
- Temperature Dependency : Reset timeout varies with temperature (typically ±25%)
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Sequencing
- Pitfall : Incorrect power sequencing causing false resets
- Solution : Ensure VCC rises monotonically during power-up; use proper decoupling capacitors
Manual Reset Implementation
- Pitfall : Poor debouncing on MR pin leading to multiple resets
- Solution : Implement hardware debouncing (RC filter) or software debouncing
Reset Output Loading
- Pitfall : Excessive capacitive loading on RESET output causing timing issues
- Solution : Limit capacitive load to <50pF; use buffer for heavy loads
### Compatibility Issues with Other Components
Microprocessor Interfaces
- Compatible with most CMOS and TTL logic families
- Ensure RESET output voltage levels match μP requirements
- Watch for push-pull vs. open-drain output configurations
Power Management ICs
- Works well with LDO regulators and switching converters
- Monitor input voltage before any series resistors or diodes
- Consider voltage drops in power distribution network
Mixed-Signal Systems
- Keep analog and digital grounds separate but properly connected
- Place CAT803 close to μP reset pin to minimize noise pickup
- Avoid routing reset lines near noisy signals (clocks, switching regulators)
### PCB Layout Recommendations
Placement Strategy
- Position CAT803 within 25mm of the microprocessor's reset pin
- Place decoupling capacitor (100nF) directly adjacent to VCC pin
- Keep manual reset circuitry away from high-frequency signals
Routing Guidelines
- Use wide traces (≥10mil) for VCC and GND connections
- Route
