Low Cost uP Supervisory Circuits# ADM705AR Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The ADM705AR is a microprocessor supervisory circuit primarily employed in embedded systems requiring reliable power monitoring and reset control. Key applications include:
Power-On Reset Generation
- Provides a clean reset signal during power-up sequences
- Ensures proper microprocessor initialization when VCC reaches stable operating levels
- Maintains reset assertion during power-up transients (typically 140ms minimum)
Battery-Powered Systems
- Monitors battery voltage levels in portable equipment
- Triggers safe shutdown procedures when voltage drops below threshold
- Prevents data corruption in non-volatile memory during brownout conditions
Industrial Control Systems
- Monitors 5V supply rails in PLCs and industrial controllers
- Provides watchdog timer functionality for system health monitoring
- Ensures reliable operation in electrically noisy environments
### Industry Applications
Automotive Electronics
- Engine control units (ECUs)
- Infotainment systems
- Body control modules
- Advantages : Wide temperature range (-40°C to +85°C), robust ESD protection
- Limitations : Not AEC-Q100 qualified for automotive safety applications
Medical Devices
- Patient monitoring equipment
- Portable diagnostic instruments
- Medical imaging systems
- Advantages : Precise voltage monitoring, low power consumption
- Limitations : Requires additional EMI filtering in sensitive applications
Consumer Electronics
- Smart home controllers
- Gaming consoles
- Set-top boxes
- Advantages : Cost-effective solution, small SOIC-8 package
- Limitations : Limited to 5V systems only
### Practical Advantages and Limitations
Advantages:
- Integrated watchdog timer with 1.6s timeout
- Manual reset input capability
- Low supply current (40μA typical)
- Precise voltage monitoring (±2% accuracy)
- Power-fail comparator for early warning
Limitations:
- Fixed 5V monitoring threshold only
- No adjustable reset timeout variants
- Limited to single-supply monitoring
- No built-in voltage reference for external use
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Reset Timing Issues
- Pitfall : Insufficient reset duration during fast power-up sequences
- Solution : Ensure minimum VCC rise time > 1ms and verify reset pulse width meets processor requirements
Watchdog Timer Misconfiguration
- Pitfall : Watchdog timeout occurring during normal operation
- Solution : Implement consistent watchdog refresh routine in firmware, accounting for interrupt latencies
Power Supply Sequencing
- Pitfall : Reset signal glitches during multi-rail power-up
- Solution : Use ADM705AR for primary 5V rail monitoring only; employ additional supervisors for other voltage rails
### Compatibility Issues
Microprocessor Interfaces
- Compatible with most 5V CMOS/TTL logic families
- Reset output suitable for active-low reset inputs (common in 80C51, 68HC11, etc.)
- May require level shifting for 3.3V processors
Mixed-Signal Systems
- Coexists well with analog components when proper decoupling is implemented
- Potential noise injection to sensitive analog circuits if layout is poor
- Recommended to separate digital and analog ground planes
Power Management ICs
- Works effectively with linear regulators (LM7805, etc.)
- Compatible with switching regulators when adequate filtering is provided
- Monitor output of regulator, not input, for accurate system voltage supervision
### PCB Layout Recommendations
Power Supply Decoupling
- Place 0.1μF ceramic capacitor within 5mm of VCC pin
- Use low-ESR capacitors for optimal transient response
- Route power traces directly from capacitor to IC pins
Signal Routing
- Keep reset output trace short and away from noisy
