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Z84C30AB6STN/a69avaiZ80 CTC CMOS VERSION
Z84C30BB6STN/a3avaiZ80 CTC CMOS VERSION


Z84C30AB6 ,Z80 CTC CMOS VERSIONapplications. The four inde- pendently programmable channels of the CTC sat- isfy common microcom ..
Z84C30BB6 ,Z80 CTC CMOS VERSIONFUNCTIONAL DESCRIPTION The 2800 CTC has four independent counter/timer channels. Each channel i ..
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Z84C30AB6-Z84C30BB6
Z80 CTC CMOS VERSION
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di;i=i'j) iwfimtggigmig
284C30
Z8OC CTC CMOS VERSION
n FOUR INDEPENDENTLY PROGRAMMABLE
COUNTER/TIMER CHANNELS, EACH WITH A
READABLE DOWNCOUNTER AND A SE-
LECTABLE 16 OR 256 PRESCALER. DOWN-
COUNTERS ARE RELOADED
AUTOMATICALLY AT ZERO COU NT
u THREE CHANNELS HAVE ZERO COUNT/TI-
MEOUT OUTPUTS CAPABLE OF DRIVING
DARLINGTON TRANSISTORS
u SELECTABLE POSITIVE OR NEGATIVE TRIG-
GER INITIATES TIMER OPERATION
n STANDARD 280C FAMILY DAISY-CHAIN IN-
TERRUPT STRUCTURE PROVIDES FULLY
VECTORED, PRIORITIZED INTERRUPTS
WITHOUT EXTERNAL LOGIC. THE CTC MAY
ALSO BE USED AS AN INTERRUPT CON-
TROLLER
u INTERFACE DIRECTLY TO THE Z800 CPU
OR-FOR BAUD RATE GENERATION - TO THE
2800 SIO
a SINGLE 5 V i 10 % POWER SUPPLY
u LOW POWER CONSUMPTION :
- 3 mA TYP, AT 4 MHz
- 4 mA TYP, AT 6 MHz
- LESS THAN 10 pA IN POWER DOWN
n EXTENDED OPERATING TEMPERATURE :
- 4OOCTO+85°C
DESCRIPTION
The 2800 CTC four-channei counter/timer can be
programmed by system software for a broad range
of counting and timing applications. The four inde-
pendently programmable channels of the CTC sat-
isfy common microcomputer system requirements
for event counting, interrupt and interval timing, and
general clock rate generation.
System design is simplified because the CTC con-
nects directly to both the CPU and the SIG with no
additional logic. In larger systems, address de-
coders and buffers may be required.
Programming the CTC is straightforward : each
channel is programmed with two bytes : a third is
necessary when interrupts are enabled. Once
started, the CTC counts down, reloads its time con-
stant automatically, and resumes counting. Soft-
ware timing loops are completely eliminated.
September 1988
DlP-28 DlP-28
(Plastic) (Ceramic)
" 'l’\ N
PLCC44
(Plastic)
(Ordering Information at the end of the datasheet)
LOGIC FUNCTIONS
’< -V Do cunncc - __
d - D, ZC/TO; - -
+-.1 D;
CPU H o, Cimnc, - _
H o. tcrTo, ' CHANNEL
H Ds SIGNALS
---- co CLtUTmis, -
_ - u, zcnoi Y-r' -*
t- ~--a- CF
---* CSo cumin;1 --
CONTROL I - - cs,
FROM --i- u, 'irsso --
- IORO
--v 56
DAISY -----v m
CHAIN ZBICJO
INYERRUPT
CONTROL
---- 4 IE
(77 A IN
ct K Vcc, GND
284C30
Interrupt processing is simplified because only one
vector need be specified ; the CTC internally gener-
ates a unique vector for each channel.
The 280C CTC requires a single + 5 V power sup-
ply and the standard 2800 single-phase system
clock. It is fabricated with n-channel silicon-gate de-
pletion-load technology, and packaged in a 28-pin
plastic or ceramic DIP.
Figure1 : Dual in Line Pin Configuration.
m E 1 " Cl Da
Ds 2 " D:
Ds C 3 26 a D,
01 C q 25 Do
GND C s 24 Cl Voc
RD C 6 " Ca CLKn’Rco
zcnoo , 22 CLKITRG,
zcrro1 C 3 184cm) 21 " CLKfTRG;
zcno, E 9 20 a cmnnc;
. NW) C 10 " Cl CS.
IEO n " D cs0
irii E " " C) R-ESE-T
IEI C 13 " D E
iii C u " Cl CLK
Figure 2 : Chip Carrier Pin Configuration.
"TCri7truJCCrTCT'CrT
‘le Ia," I! '2
tn U Jr.
NC = NO CONNECTION
4, O o Z
"..jtC1iCLcagL1.I-1tA.lu,
E 5 d, 3 I I u. 1.] L LI an
GNDC 7 19 jnc
N-C-C a in NC.
R0: 3 J7 gvcc
zcnootj IO m ch.
N-CC ll 35 DCLKITRGO
ZCIIO.E l 284C30 " jNC.
zcnozc 11 J jcuumo.
IOREE lit n jcuumcz
NC. is u jummcz
1505 )5 " :INL
~ch 29 jcs,
I8 '9 .‘J J', J 2; " " " 27 26 S-iM20
SGS-IHOMSON
Wttfil@Ell,E(en8Ct0EnC$t
FUNCTIONAL DESCRIPTION
The 2800 CTC has four independent counter/timer
channels. Each channel is individually programmed
with two words : a control word and a time-constant
word. The control word selects the operating mode
(counter or timer), enables or disables the channel
interrupt, and selects certain other operating par-
ameters. If the timing mode is selected, the control
word also sets a prescaler, which divides the sys-
tem clock by either 16 or 256. The time-constant
word is a value from 1 to 256.
During operation, the individual counter channel
counts down from the preset time constant value. In
counter mode operation the counter decrements on
each of the CLK/TRG input pulses until zero count
is reached. Each decrement is synchronized by the
system clock. For counts greater than 256, more
than one counter can be cascaded. At zero count,
the down-counter is automatically reset with the time
constant value.
The timer mode determines time interval as small
as 4 us (2800A) without additional logic or software
timing loops. Time intervals are generated by divi-
ding the system clock with a prescaler that decre-
ments a preset down-cou nter.
Thus, the time interval is an integral multiple of the
clock period, the prescalervalue (16 or 256) and the
time constant that is preset in the down-counter. A
timer is triggered automatically when its time con-
stant value is programmed, or by an external ,
CLK/TRG input.
Three channels have two outputs that occur at zero
count. The first output is a zero-count/timeout pulse
at the ZC/TO output. The fourth channel (Channel
3) does not have a ZC/TO output ; interrupt request
is the only output available from Channel 3.
The second output is Interrupt Request (INT), which
occurs if the channel has its interrupt enabled dur-
ing programming. When CPU acknowledges Inter-
rupt Request, the CTC places an interrupt vector on
the data bus.
The four channels of the CTC are fully prioritized
and fit into four contiguous slots in a standard 2800
daisy-chain interrupt structure. Channel 0 is the hig-
hest priority and Channel 3 the lowest. Interrupts
can be individually enabled (or disabled) for each of
the four channels.
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