IC Phoenix
 
Home ›  X > X1 > 10pcs of XPC855TZP50D4,mfg:FREESCALE,Quad integrated communications controller, 10/100 Mbps, 50 MHz
XPC855TZP50D4 from IC-PHOENIX Fast Delivery,Good Price
Part Number:
If you need more quantity or better price,Welcom Any inquiry.
We available via phone +865332796365 Email
XPC855TZP50D4 from FREESCALE, 10pcs , BGA,Quad integrated communications controller, 10/100 Mbps, 50 MHz
Partno Mfg Dc Qty Available
XPC855TZP50D4 FREESCALE N/a 10
XPC855TZP50D4 1pcs , BGA,Quad integrated communications controller, 10/100 Mbps, 50 MHz
XPC855TZP50D4 from MOT, Motorola 102pcs , BGA,Quad integrated communications controller, 10/100 Mbps, 50 MHz
XPC855TZP50D4 from MOTOROLA, Motorola 148pcs , BGA-357,Quad integrated communications controller, 10/100 Mbps, 50 MHz
features:• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch, without conditional execution— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches are two-way, set-associative with 128 sets.– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way, set-associative with 128 sets.– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks.2 MPC860 Family Hardware Specifications MOTOROLA Features MPC8xx core that incorporates memory management units (MMUs) and instruction anddata caches and that implements the PowePC instruction set. The communicationsprocessor module (CPM) from the MC68360 QUICC has been enhanced by the addition of2the inter-integrated controller (I C) channel. The memory controller has been enhanced,enabling the MPC860 to support any type of memory, including high-performancememories and new types of DRAMs. A PCMCIA socket controller supports up to twosockets. A real-time clock has also been integrated. Table 1 shows the functionality supported by the members of the MPC860 family.Table 1. MPC860 Family FunctionalityCache (Kbytes) Ethernet 1Part ATM SCC Ref.Instruction Data Cache 10T 10/100Cache MPC860DE 4 4 Up to 2 — — 2 1MPC860DT 4 4 Up to 2 1 yes 2 1,2,3MPC860DP 16 8 Up to 2 1 yes 2 1,2,3MPC860EN 4 4 Up to 4 — — 4 1MPC860SR 4 4 Up to 4 — yes 4 1,2MPC860T 4 4 Up to 4 1 yes 4 1,2,3MPC860P 16 8 Up to 4 1 yes 4 1,2,3MPC855T 4 4 1 1 yes 1 41Supporting documentation for these devices refers to the following:1. MPC860 PowerQUICC User’s Manual (MPC860UM/D, Rev. 1).2. MPC8XX ATM Supplement (MPC860SARUM/AD).3. MPC860T (Rev. D), Fast Ethernet Controller Supplement (MPC860TREVDSUPP). 4. MPC855T User’s Manual (MPC855TUM/D, Rev. 1).Part II Features– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — Instruction and data caches are two-way, set-associative, physically addressed, LRU replacement, and lockable on-line granularity.— MMUs with 32-entry TLB, fully associative instruction, and data TLBs— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups— Advanced on-chip-emulation debug mode• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)• 32 address lines• Operates at up to 80 MHz• Memory controller (eight banks)— Contains complete dynamic RAM (DRAM) controller— Each bank can be a chip select or RAS to support a DRAM bank— Up to 15 wait states programmable per memory bank— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices.— DRAM controller programmable to support most size and speed memory interfaces— Four CAS lines, four WE lines, one OE line— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)— Variable block sizes (32 Kbyte to 256 Mbyte)— Selectable write protection— On-chip bus arbitration logic• General-purpose timers— Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting— Interrupt can be masked on reference match and event capture• System integration unit (SIU)— Bus monitor— Software watchdog— Periodic interrupt timer (PIT)— Low-power stop mode— Clock synthesizerMOTOROLA MPC860 Family Hardware Specifications 3 Thermal Characteristics” 7Part V, “Power Dissipation” 8Part VI, “DC Characteristics” 9Part VII, “Thermal Calculation and Measurement” 10Part VIII, “Layout Practices” 13Part IX, “Bus Signal Timing” 13Part X, “IEEE 1149.1 Electrical Specifications” 41Part XI, “CPM
XPC855TZP66D3 MOT

ic,good price


TEL:86-533-2796365      FAX:86-533-2716790
   

©2018 IC PHOENIX CO.,LIMITED