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VV6404C001 from ST, ST Microelectronics 1000pcs,CIF resolution colour digital CMOS image sensor
Partno Mfg Dc Qty Available
VV6404C001 ST N/a 1000
VV6404C001 from VISION, 11000pcs , LCC,CIF resolution colour digital CMOS image sensor
General Description . . . 275.2 Serial Communication Protocol . .275.3 Data Format .275.4 Message Interpretation .285.5 The Programmers Model . . . . . . .295.5.1 DeviceH [000_00002] and DeviceL [000_ 00012] . . . 315.5.2 Status0 [000_00102] .315.5.3 Line_count_H [000_00112] & Line_count_L [000_01002] . . . . . 315.5.4 Setup0 [001_00002] .325.5.5 Setup1 [001_00012] .325.5.6 Setup2 [001_00102] .335.5.7 Setup4 [001_01002] .335.5.8 Setup5 [001_01012] .345.5.9 Exposure Control Registers [010_00002] - [010_10012] . . . . . . 355.5.10 ADC Setup Register AS0 [111_01112] . . 375.6 Types of messages . . . . 385.6.1 Single location, single data write 38CD5404-6404F-A 2/54VV5404 & VV64045.6.2 Single location, single data read. 385.6.3 No data write followed by same location read . . . . . . 385.6.4 Same location multiple data write. . . . . . . . 395.6.5 Same location multiple data read . . . . . . . 395.6.6 Multiple location write 405.6.7 Multiple location read .405.7 Serial Interface Timing .416. Clock Signal .426.8 Synchronising 2 or More Cameras 437. Detailed specifications .457.1 General . . . . .457.2 DC characteristics . . . . . 458. Physical . . . . .468.1 Pinout Diagram . . . . . . . 468.2 Signal Names 478.3 48LCC Mechanical Dimensions . .498.4 VV6404 Sensor Support Circuit Schematic Diagram . .508.5 Sensor Support Circuit Component List . . .509. Ordering Information . . 52CD5404-6404F-A 3/54VV5404 & VV64041. IntroductionVV5404 and VV6404 are CIF format CMOS image sensors capable of outputing digital pixel data at frame rates, of upto 30 frames per second. The VV5404 is a monochrome part, while the VV6404 has a colour filter applied over the sensor array.Important: The VV6404 sensor’s video data stream only contains raw colourised pixel data. A colour co-processor is required to generate for example either a CIF or a QCIF format YUV colour image.The 356 x 292 pixel sensors have an on-chip 8-bit analogue to digital converter (Figure 1). The sensors offer veryflexible digital interface, the main components of which are listed below:1. A tri-stateable 4-wire data bus (D[3:0]) for sending both video data and embedded timing references.2. A data qualification clock, QCK, which can be programmable via the serial interface to behave in a number of different ways (Tri-stateable).3. A frame start signal, FST (Tri-stateable).4. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device.5. The ability to synchronise the operation of multiple cameras - synchronisation input, SIN.An 8-bit pixel value is transmitted across the 4 wire tri-stateable databus as series pair of 4-bit nibbles, most significant nibble first. Along within the pixel data, codes representing the start and end frames and the start and end of lines are embedded within the video data stream to allow the video processor to synchronise with video data the camera module is generating. Section 4. defines the format for the output video datastream.CLKI SERIALIMAGEBLACK EXPOSURESDAINTER-CLKOCALIBRATION FORMAT REGISTERSFACESCLSIND[3:0]OUTPUTQCKVERTICALFORMATPHOTO DIODESHIFTFSTARRAYREGISTEROEB8-bitADCSAMPLE & HOLDANALOGVOLTAGEGAINREFS.HORIZONTAL SHIFTSTAGEREGISTERFigure 1 : General description . . . . .94.2 Embedded control data . .94.2.1 The combined escape and sync character . 94.2.2 The command word . . . 94.2.3 Supplementary Data .134.3 Video timing reference and status/configuration data . .134.3.1 Blank lines . 144.3.2 Black line timing . . . . .144.3.3 Valid video line timing 144.3.4 Start of frame line timing . . . . . . 144.3.5 End of frame line timing . . . . . . .144.4 Detection of sensor using data bus state . . .144.5 Resetting the Sensor Via the Serial Interface 144.6 Power-up, Low-power and Sleep modes . . .144.6.1 Power-Up/Down (Figure 12) . . . 184.6.2 Low-Power Mode (Figure 10) . .184.6.3 Sleep Mode (Figure 11) . . . . . . .184.6.4 Application of the system clock during sensor low-power modes . . . . . . . 224.7 Qualification of Output Data . . . . . 224.7.1 Using the External Clock signal applied to CKI . . . . . 224.7.2 Data Qualification Clock, QCK . .224.7.3 Frame Start Signal, FST . . . . . . 225. Serial Control Bus . . . . 275.1
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