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VNS1NV04D13TRSTN/a4036avaiOMNIFET II: FULLY AUTOPROTECTED POWER MOSFET


VNS1NV04D13TR ,OMNIFET II: FULLY AUTOPROTECTED POWER MOSFETFEATURES - OVERTEMPERATURE AND SHORT CIRCUITPROTECTION: these are based on sensing theDuring normal ..
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VNS1NV04D13TR
OMNIFET II: FULLY AUTOPROTECTED POWER MOSFET
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VNS1NV04D
"OMNIFET ll":
FULLY AUTOPROTECTED POWER MOSFET
TYPE RDS(on) llim Vclamp
VNS1NV04D 250 mo (*) 1.7A(*) 40V(*)
i') Pereach device
- LINEAR CURRENT LIMITATION
- THERMAL SHUT DOWN
- SHORT CIRCUIT PROTECTION
- INTEGRATED CLAMP
. LOW CURRENT DRAWN FROM INPUT PIN
l DIAGNOSTIC FEEDBACK THROUGH INPUT
- ESD PROTECTION
- DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
I COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VNS1NV04D is a device formed by two
monolithic OMNIFET ll chips housed in a
standard SO-8 package. The OMNIFET II are
designed in STMicroelectronics VIPower M0-3
BLOCK DIAGRAM
Technology: they are intended for replacement of
standard Power MOSFETS from DC up to 50KHz
applications. Built in thermal shutdown, linear
current limitation and overvoltage clamp protects
the chip in harsh environments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
OVERVOLTAGE
q CLAMP
INPUT1 GATE I _ J1
CONTROL TCt
LINEAR
TEMPERATURE
_- CURRENT
OVER LIMITER
SOURCE1
DRAIN2
OVERVOLTAGE
SOURCE2
GATE INPUT2
CONTROL H U
TEMPERATURE
LINEAR
CURRENT -
LIMITER
February 2003
VNS1NV04D
ABSOLUTE MAXIMUM RATING
Symbol Parameter Value Unit
VDSn Drain-source Voltage (Van=0V) Internally Clamped V
VINn Input Voltage Internally Clamped V
IINn Input Current +/-20 mA
Rm MINn Minimum Input Series Impedance 330 n
an Drain Current Internally Limited A
IRn Reverse DC Output Current -3 A
VESDI Electrostatic Discharge (R=1.5KQ, C=100pF) 4000 V
VESDZ Electrostatic Discharge on output pins only (R=330f2, C=150pF) 16500 V
Ptot Total Dissipation at Tc=25°C 4 W
Tj Operating Junction Temperature Internally limited ''C
Tc Case Operating Temperature Internally limited "C
Tstg Storage Temperature -55 to 150 "C
CONNECTION DIAGRAM (TOP VIEW)
SOURCE1 E 1 U 8 [I DRAIN1
INPUT 1 , [I DRAIN 1
SOURCE 2 E D DRAIN 2
INPUT 2 l] 4 5 D DRAIN 2
CURRENT AND VOLTAGE CONVENTIONS
liNI RIN1 ID1
—:}—D INPUT1 DRAIN1 L |——'
VIN1 IN2 - IN2 I D2 VDs1
fl] INPUT 2 DRAIN 2 E]—
SOURCE 1 sou RCE 2 V931
2/14 gr,
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