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VIPER53STN/a1200avaiOFF LINE PRIMARY SWITCH
VIPER53DIPST ?N/a5000avaiOFF LINE PRIMARY SWITCH
VIPER53DIPSTN/a10000avaiOFF LINE PRIMARY SWITCH
VIPER53SPSTMicroelectronicsN/a50avaiOFF LINE PRIMARY SWITCH
VIPER53SP13TRSTN/a7200avaiOFF LINE PRIMARY SWITCH


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VIPER53-VIPER53DIP-VIPER53SP-VIPER53SP13TR
OFF LINE PRIMARY SWITCH
June 2004 1/24
VIPer53DIP
VIPer53SP

OFF LINE PRIMARY SWITCH
TYPICAL OUTPUT POWER CAPABILITY

Note: Above power capabilities are given under adequate
thermal conditions
FEATURES
SWITCHING FREQUENCY UP TO 300 kHz CURRENT LIMITATION CURRENT MODE CONTROL WITH
ADJUSTABLE LIMITATION SOFT START AND SHUT DOWN CONTROL AUTOMATIC BURST MODE IN STAND-BY
CONDITION (“BLUE ANGEL” COMPLIANT) UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS HIGH VOLTAGE STARTUP CURRENT
SOURCE OVERTEMPERATURE PROTECTION OVERLOAD AND SHORT-CIRCUIT CONTROL
DESCRIPTION

The VIPer53 combines in the same package an
enhanced current mode PWM controller with a
high voltage MDMesh Power Mosfet. Typical
applications cover off line power supplies with a
secondary power capability ranging up to 30W in
wide range input voltage or 50W in single
European voltage range and DIP-8 package, with
the following benefits: Overload and short circuit controlled by
feedback monitoring and delayed device reset. Efficient standby mode by enhanced pulse
skipping. Primary regulation or secondary loop failure
protection through high gain error amplifier.
BLOCK DIAGRAM
VIPer53DIP / VIPer53SP
PIN FUNCTION
CURRENT AND VOLTAGE CONVENTIONS
CONNECTION DIAGRAM
ORDER CODES
VIPer53DIP / VIPer53SP
ABSOLUTE MAXIMUM RATINGS

Note:1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 kΩ should be inserted in
series with the TOVL pin.
THERMAL DATA

Note:2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 μm thick) connected to the DRAIN pin. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 μm thick) connected to the device tab.
VIPer53DIP / VIPer53SP
ELECTRICAL CHARACTERISTICS (Tj=25°C, VDD=13V, unless otherwise specified)

POWER SECTION
Note4. On clamped inductive load This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon
and the following formula:
OSCILLATOR SECTIONton---CEon 3002V DSon
300----------------1.5 ⋅=
VIPer53DIP / VIPer53SP
ELECTRICAL CHARACTERISTICS (Tj=25°C, VDD=13V, unless otherwise specified)

SUPPLY SECTION
ERROR AMPLIFIER SECTION
Note6. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should always be present on
the COMP pin.
VIPer53DIP / VIPer53SP
ELECTRICAL CHARACTERISTICS (Tj = 25 °C, VDD = 13 V, unless otherwise specified)

PWM COMPARATOR SECTION
OVERLOAD PROTECTION SECTION
Note7. VCOMPovl is always lower than VCOMPhi.
OVERTEMPERATURE PROTECTION SECTION
VIPer53DIP / VIPer53SP
Figure 1: Rise and Fall Time
Figure 2: Start-up VDD Current
Figure 3: Output Characteristics
Figure 4: Overload event
VIPer53DIP / VIPer53SP
Figure 5: Thermal Shutdown
Figure 6: Shut Down Action
Figure 7: Overvoltage Event
Figure 8: Comp Pin Gain and Offset
VIPer53DIP / VIPer53SP
Figure 9: Oscillator Schematic and Settings
VIPer53DIP / VIPer53SP
Figure 10: Error Amplifier Transfer Function
Figure 11: Blanking Time
VIPer53DIP / VIPer53SP
Figure 12: Typical Frequency Variation vs. Junction Temperature
Figure 13: Typical Current Limitation vs. Junction Temperature
VIPer53DIP / VIPer53SP
Figure 14: Off Line Power Supply With Auxiliary Supply Feedback
PRIMARY REGULATION CONFIGURATION
EXAMPLE

The schematic on figure 14 delivers a fixed output
voltage by using the internal error amplifier of the
device in a primary feedback configuration. The
primary auxiliary winding provides a voltage to the
VDD pin, and is automatically regulated at 15V
thanks to the internal error amplifier connected on
this pin. The secondary voltage has to be adjusted
through the turn ratio of the transformer between
auxiliary and secondary.
The error amplifier of the VIPer53 is a
transconductance one: its output is a current
proportional to the difference of voltage between
the VDD pin and the internal trimmed 15V
reference, i.e. the error voltage. As the
transconductance value is set at a relatively low
value to control the overall loop gain and insure
stability, this current has to be integrated by a
capacitor (C7 in the above schematic). When the
steady state operation is reached, this capacitor
blocks any DC current from the COMP pin and
imposes a nil error voltage. Therefore, the VDDvoltage is accurately regulated to 15V.
This results in a good load regulation, which
depends only on transformer coupling and output
diodes impedance. The current mode structure
takes care of all incoming voltage changes, thus
providing at the same time an excellent line
regulation.
The switching frequency can be set to any value
through the choice of R3 and C5. This allows to
optimize the efficiency of the converter by adopting
the best compromise between switching losses,
EMI (Lower with low switching frequencies) and
transformer size (Smaller with high switching
frequencies). For an output power of a few watts,
typical switching frequencies are comprised
between 20 kHz and 40 kHz because of the small
size of the transformer. For higher power, 70 kHz
to 130 kHz are generally chosen.
The value of the compensation resistor R5 sets the
dynamic behavior of the converter. It can be
adjusted to provide the best compromise between
stability and recovering time with fast load
changes.
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