USBLC6-4SC6 ,VERY LOW CAPACITANCE ESD PROTECTIONApplicationSpecific Discrete dedicated to ESD protection ofhigh speed interfaces, such as USB2.0, E ..
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USBLC6-4-USBLC6-4SC6
VERY LOW CAPACITANCE ESD PROTECTION
1/10
USBLC6-4SC6VERY LOW CAPACITANCE
ESD PROTECTION
REV. 1
December 2004
MAIN APPLICATIONS USB2.0 ports up to 480Mb/s (high speed) Backwards compatible with USB1.1 low and
full speed Ethernet port: 10/100Mb/s SIM card protection Video line protection Portable electronics
DESCRIPTIONThe
USBLC6-4SC6 is a monolithic ApplicationSpecific Discrete dedicated to ESD protection of
high speed interfaces, such as USB2.0, Ethernet
links and Video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
FEATURES 4 data lines protection Protects VBUS at both 5V (low and full speed)
and 3.3V (high speed) operations Very low capacitance: 3pF typ. SOT23-6L package
BENEFITS Very low capacitance between lines to GND for
optimized data integrity and speed Low PCB space consuming, 9mm² maximum
foot print Enhanced ESD protection IEC61000-4-2 level 4 compliance guaranteed
at device level, hence greater immunity at
system level ESD protection of VBUS. Allows ESD current
flowing to Ground when ESD event occurs ondata line High reliability offered by monolithic integration Low leakage current for longer operation of
battery powered devices Fast response time Consistent D+ / D- signal balance:
- Best capacitance matching tolerance
I/O to GND = 0.015pF
- Compliant with USB 2.0 requirements < 1pF
Table 1: Order CodeASD™
Figure 1: Functional Diagram
TM: ASD is a trademark of STMicroelectronics.
COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 level4:
15kV (air discharge)
8kV (contact discharge)
USBLC6-4SC6
Table 2: Absolute Ratings
Table 3: Electrical Characteristics (Tamb = 25°C)
USBLC6-4SC63/10
Figure 2: Capacitance versus voltage (typical
values)
Figure 3: Line capacitance versus frequency
(typical values)
Figure 4: Relative variation of leakage current
versus junction temperature (typical values)
Figure 5: Frequency response
USBLC6-4SC6
TECHNICAL INFORMATION
1. SURGE PROTECTIONThe USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage VCL can be calculated as follow :
VCL + = V BUS + VF for positive surges
VCL- = - VF for negative surges
with: VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
We assume that the value of the dynamic resistance of the clamping diode is typically: = 1.4Ω and VT = 1.2V.
For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330Ω), VBUS = +5V, and if in first
approximation, we assume that : Ip = Vg / Rg = 24A.
So, we find:CL + = +39V
VCL- = -34V
Note: the calculations do not take into account phenomena due to parasitic inductances.
2. SURGE PROTECTION APPLICATION EXAMPLEIf we consider that the connections from the pin V BUS to VCC and from GND to PCB GND are done by
two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks
are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the
voltage VCL has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping
voltage will be :CL + = +39 + 144 = 183V
VCL- = -34 - 144 = -178V
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good
ESD protection”).
Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout
USBLC6-4SC65/10
3. HOW TO ENSURE A GOOD ESD PROTECTIONWhile the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the
layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power
supply +VCC and from the V BUS pin to GND must be as short as possible to avoid overvoltages due to
parasitic phenomena (see figure 6).
It’s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the
ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short enough, we
recommend to put close to the USBLC6-4SC6, between VBUS and ground, a capacitance of 100nF to
prevent from these kinds of overvoltage disturbances (see figure 7).
The add of this capacitance will allow a better protection by providing during surge a constant voltage.
The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations
described above.
IMPORTANT:A main precaution to take is to put the protection device closer to the disturbance source (generally the
connector).
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
Figure 7: ESD behavior: optimized layout and
add of a capacitance of 100nF
Figure 8: ESD behavior: measurements
conditions (with coupling capacitance)
Figure 9: Remaining voltage after the
USBLC6-4SC6 during positive ESD surge
Figure 10: Remaining voltage after the
USBLC6-4SC6 during negative ESD surge
USBLC6-4SC6
4. CROSSTALK BEHAVIOR
4.1. Crosstalk phenomena
Figure 11: Crosstalk phenomenaThe crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β21)
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load RL2 is α2VG2 , in fact the real voltage at this point has got an extra value β21VG1.
This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.
This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage
signal or high load impedance (few kΩ).
Figure 12: Analog crosstalk measurementsFigure 12 gives the measurement circuit for the analog application. In usual frequency range of analog
signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).
Figure 13: Analog crosstalk resultsAs the USBLC6-4SC6 is designed to protect high
speed data lines, it must ensure a good transmis-
sion of operating signals. The frequency response
(figure 5) gives attenuation information and shows
that the USBLC6-4SC6 is well suitable for data
line transmission up to 480 Mbit/s while it works
as a filter for undesirable signals like GSM
(900MHz) frequencies, for instance.
