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UC3842BN ,HIGH PERFORMANCE CURRENT MODE PWM CONTROLLEROrder this document by UC3842B/D** ** * ** * * **HIGH PERFORMANCEThe UC3842B, UC3843B series are h ..
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TUA6030
Analog Terrestrial _ Cable Tuner Systems
Wireless Components
3-Band TV Tuner IC
TUA6030, TUA6032 Version 2.1
Specification July 2001
Edition 03.99
Published by Infineon Technologies AG
Balanstraße 73,
81541 München© InfineonTechnologiesAG 04.07.01.
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Product Info
Product Info
General DescriptionThe TUA6030, TUA6032 devices com-
bine a mixer-oscillator block with a dig-
itally programmable phase locked loop
(PLL) for use in TV and VCR tuners.
FeaturesGeneralSuitable for PAL/NTSC and Digital
Video BroadcastingWideband AGC detector for inter-
nal tuner AGC
− 5 programmable take-over points
− 2 programmable time constantsFull ESD protection
Mixer/OscillatorHigh impedance mixer input (com-
mon emitter) for LOW bandLow impedance mixer input (com-
mon base) for MID bandLow impedance mixer input (com-
mon base) for HIGH band2 pin oscillator for LOW band2 pin oscillator for MID band4 pin oscillator for HIGH band
IF-AmplifierIF preamplifier with symmetrical
75 Ω output impedance able to
drive a SAW filter (500 Ω//40 pF)
PLL4 independent I2C addressesI2C bus protocol compatible with
3.3 V and 5V micro-controllers up
to 400 kHzShort lock-in timeHigh voltage VCO tuning output4 PNP ports3 NPN ports1 NPN port/ADC inputInternal LOW/MID/HIGH band
switchLock-in flagProgrammable reference divider
ratio (24, 64, 80, 128)Programmable charge pump
current
Application-The IC is suitable for PAL and
NTSC tuners in TV- and VCR-sets
or set-top receivers for analog TV
and Digital Video Broadcasting. The AGC stage makes the
tuner AGC independent of the
Video-IF AGC.
Ordering Information
Table of ContentsTable of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72.1Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.3Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-113.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.2Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.3Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.4Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-234-1Application Circuit for NTSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
4-2Application Circuit for PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-265.1Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27
5.1.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27
5.1.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29
5.1.3AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30
5.2Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-39
Table 5-4Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . .5-39
Table 5-5Description of Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-39
Table 5-6Address selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
Table 5-7Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
Table 5-8Reference divider ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
Table 5-9AGC take-over point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
Table 5-10A to D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-41
Table 5-11Defaults at power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . .5-41
Table 5-12Internal band selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-41
5.3I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-42
5.4Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-43
5.4.1Input admittance (S11) of the LOW band mixer (40 to 140 MHz). . .5-43
5.4.2Input impedance (S11) of the MID band mixer (150 to 455 MHz) . .5-43
5.4.3Input impedance (S11) of the HIGH band mixer (450 to 865 MHz) .5-44
Table of Contents5.4.4Output admittance (S22) of the of the Mixer output (30 to 50 MHz).5-44
5.4.5Output impedance (S22) of the IF amplifier (30 to 50 MHz). . . . . . .5-45
5.5Measurement Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-46
5.5.1Gain (GV) measurement in LOW band. . . . . . . . . . . . . . . . . . . . . . .5-46
5.5.2Gain (GV) measurement in MID and HIGH bands. . . . . . . . . . . . . .5-46
5.5.3Matching circuit for optimum noise figure in LOW band. . . . . . . . . .5-47
5.5.4Noise figure (NF) measurement in LOW band. . . . . . . . . . . . . . . . .5-47
5.5.5Noise figure (NF) measurement in MID and HIGH bands . . . . . . . .5-48
5.5.6Cross modulation measurement in LOW band. . . . . . . . . . . . . . . . .5-48
5.5.7Cross modulation measurement in MID and HIGH bands . . . . . . . .5-49
5.5.8Ripple susceptibility measurement. . . . . . . . . . . . . . . . . . . . . . . . . .5-49
Product Description2.1Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.3Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Product Description
2.1OverviewThe TUA6030, TUA6032 devices combine a mixer-oscillator block with a digi-
tally programmable phase locked loop (PLL) for use in TV and VCR tuners.
The mixer-oscillator block includes three balanced mixers (one mixer with an
unbalanced high-impedance input and two mixers with a balanced low-imped-
ance input), two 2-pin asymmetrical oscillators for the LOW and the MID band,
one 4-pin symmetrical oscillator for the HIGH band, an IF amplifier, a reference
voltage, and a band switch.
The PLL block with four independently selectable chip addresses forms a digit-
ally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL per-
mits precise setting of the frequency of the tuner oscillator up to 1024 MHz in
increments of 31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by
a microprocessor via an I2C bus. The device has 8 output ports, one of them
(P6) can also be used as ADC input port. A flag is set when the loop is locked.
The lock flag can be read by the processor via the I2C bus.
2.2Features
GeneralSuitable for PAL/NTSC and Digital Video BroadcastingWideband AGC detector for internal tuner AGC
− 5 programmable take-over points
− 2 programmable time constantsFull ESD protection
Mixer/OscillatorHigh impedance mixer input (common emitter) for LOW bandLow impedance mixer input (common base) for MID bandLow impedance mixer input (common base) for HIGH band2 pin oscillator for LOW band2 pin oscillator for MID band4 pin oscillator for HIGH band
IF-AmplifierIF preamplifier with symmetrical 75 Ω output impedance able to drive a
SAW filter (500 Ω//40 pF)
PLL4 independent I2C addressesI2C bus protocol compatible with 3.3 V and 5V micro-controllers up to
400 kHz
Product DescriptionShort lock-in timeHigh voltage VCO tuning output4 PNP ports3 NPN ports1 NPN port/ADC inputInternal LOW/MID/HIGH band switchLock-in flagProgrammable reference divider ratio (24, 64, 80, 128)Programmable charge pump current
2.3ApplicationThe IC is suitable for PAL and NTSC tuners in TV- and VCR-sets or cable
set-top receivers for analog TV and Digital Video Broadcasting. The AGC stage makes the tuner AGC independent of the Video-IF AGC.
Recommended band limits in MHz:
Note: Tuning margin of K3 MHz not included.
Functional Description3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.2Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.3Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.4Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
Functional Description
3.1Pin Configuration
TUA6030 Pin_config
Figure 3-1Pin Configuration TUA6030
TUA6032 Pin_config
Figure 3-2Pin Configuration TUA6032
Functional Description
3.2Pin Definition and Function
Remark: First pin number refers to TUA6030, second to TUA6032
Functional Description
Functional Description
Functional Description
Functional Description
Functional Description
Functional Description
3.3Block Diagram
Remark: First pin number refers to TUA6030, second to TUA6032
TUA6030_1 BlockDiag
Figure 3-3Block Diagram
Functional Description
3.4Circuit Description
3.4.1Mixer-Oscillator block
The mixer-oscillator block includes three balanced mixers (one mixer with an
unbalanced high-impedance input and two mixers with a balanced low-imped-
ance input), two 2-pin asymmetrical oscillators for the LOW and the MID band,
one 4-pin symmetrical oscillator for the HIGH band, an IF amplifier, a reference
voltage, and a band switch.
Filters between tuner input and IC separate the TV frequency signals into three
bands. The band switching in the tuner front-end is done by using three PNP
port outputs. In the selected band the signal passes a tuner input stage with a
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the mixer
input of the IC which has in case of LOW band a high-impedance input and in
case of MID or HIGH band a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced mixer output pair by means of a parallel
tuned circuit. The following IF amplifier is capacitively coupled to the mixer out-
puts and has a low output impedance to drive the SAW filter directly.
3.4.2PLL block
The oscillator signal is internally DC-coupled as a differential signal to the pro-
grammable divider inputs. The signal subsequently passes through a program-
mable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency/phase detector with a reference frequency fref = 31.25, 50, 62.5 or
166.7 kHz. This frequency is derived from an unbalanced, low-impedance 4
MHz crystal oscillator (pin XTAL) divided by 128, 80,64 or 24. The reference fre-
quencies will be different with a quartz other than 4 MHz.
The phase detector has two outputs which drive two current sources of a charge
pump. If the negative edge of the divided VCO signal appears prior to the neg-
ative edge of the reference signal, the positive current source pulses for the
duration of the phase difference. In the reverse case the negative current
source pulses. If the two signals are in phase, the charge pump output (CP)
goes into the high-impedance state (PLL is locked). An active low-pass filter
integrates the current pulses to generate the tuning voltage for the VCO (inter-
nal amplifier, external pull-up resistor at VT and external RC circuitry). The
charge pump output is also switched into the high-impedance state if the control
bits T2, T1,T0 = 0, 1, 0. Here it should be noted, however, that the tuning volt-
age can alter over a long period in the high impedance state as a result of self
discharge in the peripheral circuity. VT may be switched off by the control bit OS
to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33V (VTH).
Functional Description
By means of control bit CP the pump current can be switched between two val-
ues by software. This programmability permits alteration of the control response
of the PLL in the locked-in state. In this way different VCO gains can be com-
pensated, for example.
The software controlled ports P0 to P7 are general purpose open-collector out-
puts. The test bits T2, T1, T0 =1, 0, 0 switch the test signals fdiv (divided input
signal) and fref (i.e.4 MHz / 64) to P4 and P5 respectively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, if
FL = 1, the maximum deviation of the input frequency from the programmed fre-
quency is given by
Δf = ± IP ∗ (KVCO / fXTAL) ∗ (C1+C2) / (C1∗C2)
where IP is the charge pump current, KVCO the VCO gain, fXtal the crystal oscil-
lator frequency and C1, C2 the capacitances in the loop filter (Chapter 4). As the
charge pump pulses at i.e. 62.5 kHz (= fref), it takes a maximum of 16 μs for FL
to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144 μs for FL to be set after the loop regains lock.
3.4.3AGC
The wide-band AGC stage detects the level of the IF output signal and gener-
ates an AGC voltage for gain control of the tuner input transistors. The AGC
take-over and the time constant are selectable by the I2C bus.
3.4.4I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL). Pin SDA functions as an input
or output depending on the direction of the data (open collector, external pull-
up resistor). Both inputs have a hysteresis and a low-pass characteristic, which
enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are high). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes low, while SCL remains high. Stop condition: SDA goes high while
Functional Description
SCL remains high. All further information transfer takes place during SCL = low,
and the data is forwarded to the control logic on the positive clock edge.
The table ’Bit Allocation’ (see Table 5-4 Bit Allocation Read / Write on page 39)
should be referred to for the following description. All telegrams are transmitted
byte-by-byte, followed by a ninth clock pulse, during which the control logic
returns the SDA line to low (acknowledge condition). The first byte is comprised
of seven address bits. These are used by the processor to select the PLL from
several peripheral components (address select). The LSB bit (R/W) determines
whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte. Appropriate setting of the test bits will decide whether the band-
switch byte or the auxiliary byte will be transmitted (see Table 5-7 Test modes on
page 40).
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists of three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS
(see Table 5-6 Address selection on page 40).
While the supply voltage is applied, a power-on reset circuit prevents the PLL
from setting the SDA line to low, which would block the bus. The power-on reset
flag POR is set at power-on and if VCC falls below 3.2 V. It will be reset at the
end of a READ operation.
Applications4.1Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
4-1Application Circuit for NTSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
4-2Application Circuit for PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25
Applications
4.1Circuits
Remark: Pinning refers to TUA6030
App Circuit Ntsc
Figure 4-1Application Circuit for NTSC
Applications
Remark: Pinning refers to TUA6030
App Circuit PAL
Figure 4-2Application Circuit for PAL
