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TS7515CPSTN/a37avaiSINGLE CHIP DPSK AND FSK MODEM


TS7515CP ,SINGLE CHIP DPSK AND FSK MODEM£77 MU©E§©EIL SGS-THOMSON Eflajii(Wl?il(f)E0(%) TS751 5 SINGLE CHIP DPSK AND FSK MODEM ..
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TS7515CP
SINGLE CHIP DPSK AND FSK MODEM
Iiiii'
SGScfiRlOiNSOR]
[i)ji][j(B0io20)EUjiitrij12(2)Mll(f)g)
TS751 5
SINGLE CHIP DPSK AND FSK MODEM
n MONOLITHIC DEVICE (INCLUDES BOTH
TRANSMIT AND RECEIVE FILTERS)
II MIXING ANALOG AND DIGITAL TECHNICS
1: STANDARD LOW COST CRYSTAL
(4.9152MHz)
II AVAILABLE CLOCK FOR MICROPROCES-
SOR AT 4.9152MH2
n LOW POWER DISSIPATION
(CMOS technology)
tt SHARP ADJACENT CHANNEL REJECTION
u FIXED COMPROMIZE EQUALIZATION IN
TRANSMITTER AND RECEIVER
II TEST LOOPS (local analog, local digital and
remote digital loopbacks)
II CARRIER DETECTION OUTPUT
n CCITT AND BELL SIGNALING TONE
n 1200BPS AND GOOBPS BIT SYNCHRONOUS
FORMAT IN DPSK
n 1200BPS AND 6OOBPS +1%, -2.5% OR
+2.3%, -2.5% CHARACTER ASYNCHRO-
NOUS FORMAT (8, 9, 10 or 11 bits) IN DPSK
u 0 TO SOOBPS IN FSK
n AUTOMATIC DIAL LINE MONITORING CAPA-
BILITY
n BREAK SIGNAL SUPERVISION
" EXTERNAL VOICE BAND TONE FILTERING
AVAILABLE (Le. 550Hz or DTMF)
n CMOS AND TTL COMPATIBLE
n DIRECT INTERFACE TO STANDARD MICRO-
PROCESSOR FAMILIES
DESCRIPTION
The TS7515 is a single chip DPSK and FSK voice-
band modem, compatible with the BELL 103, 212A
and CCITT v.22 A/B recommended standards.
MAIN OPERATING MODES
It Standard selection (Bell 212A/Bell 103N.22)
n Answer tone selection (2100 or 2225Hz)
n Low speed mode selection
a Channel selection (answer/originate)
n Synchronous/asynchronous mode selection
I: 8 bits to 11 bits word length selection in char-
acter asynchronous format mode
June 1995
I: 792923 DUEBLEB 6Ti cn
u Overspeed selection in character asynchro-
nous format mode
a Scrambler selection
I 1800Hz guard tone selection in v.22
a Test loop selection (Digital/Analog)
(Plastic Package)
ORDERING INFORMATION
Part Number "'ErJ,t""' Package
TS7515CP 0 to +70% DIP28
TS7515IP -25 to +85°C DIP28
PIN CONNECTIONS
V+ l: 1 1,..,.,.Y 28 Cl XTAL OUT
HE E 2 27 j XTALIN
C/B E 3 26 l] CLK
A/S I 4 25 Cl TxSCLK
i E 5 24 C) TxCLK
035 D 6 23 l] TxD
BRS l: 7 22 C) iiiE
RxD l: 8 21 TE
RxCLK CC 9 20 GND
TEST I 10 19 j 310
I565 E 11 18 C) RAI
CLS C 12 17 C) EXI
RDI 1: 13 16 Cl ATO
RFO l: 14 15 Ci V-
7515-01.TBL
751 5-01 EPS
T3751 5
PIN DESCRIPTION
Pin o . . .
Name Type N Function Description
COMMON SECTION (supply, clock, handshaking and mode selection)
V + I 1 Positive Power Supply +5V
V‘ l 15 Negative Power Supply -5V
GND l 20 Ground 0V
This pin gorresponds to Ithe inp‘ultJ of the oscillgtor. It is noamally
. connecte to an externa crysta ut may aso e connecte to a
XIN I 27 Oscillator Input pulse generator. The nominal frequency of the oscillator is
4.9152MHz.
. This pin corresponds to the output of an inverter with sufficient loop
XOUT O 28 Oscillator Output gain to start and maintain the crystal oscillating.
This pin delivers a clock signal, the frequency of which is the crystal
CLK C) 26 Clock frequency. It may be used as a buffered clock a microcontroller.
6/8 I 3 CCITT/BELL Selection 2igtlIrdet,t,igeate.cts the features corresponding to CCITT
_ This three-state input selects the synchronous bit format or the
AIS l 4 As nggtrt,rggiLior, asynchronous characterformat mode in DPSKtransmission. This
y input allows also character length selection (refer to table 8).
CLS t 12 Character L en gth "(2idrint'luttai'telt' the character length in conjunction with A/S input
.. . This input selects the over-speed in asynchronous character format
OSE I 6 Over speed Selection mode required by CCITT recommendation (refer to table 8).
. . A Logic "O'' on this input turns chip on1200 bpssate. A logic "1" turns
BRS I 7 Binary Rate Selection the chip on 600bps or 0-300bps according to cm selection.
- . . A logic "0" on this input turns the chip on answer mode, A logic "1"
NO l 19 Answer/Orig, Selection turns the chip on originate mode.
'E l 5 Test Loop Selection This three-state input, selects the test loops mode (refer to table 6).
TRANSMIT SECTION
Data bits to be (tjransmitted are serially presented on thisrllttptg. A
. mark correspon s to a logic "1" and a space to a ogic "O". is ata
TxD I 23 Transmit Data determines which phase or frequency appears at any instant at the
ATO pin in DPSK or FSK modes.
. The analog output is the modulated carrier or the answer tone to be
ATO O 16 Anak8gg1tnsmit conditionned and sent over the phone line mixed with the filtered
p signal from EXI.
This analog input allows external tone to be filtered by atLinternal
EXI I 17 External Tone Input low-pass filter. Filtered signal appears at ATO whatever RTS,
A logic "0" on this inpuLinstructs the chip to enter answer signaling
ATE I 2 AnswerTone Enable tone mode according C/B selection. A logic "I" turns the chip on
transmit data mode (refer to table 9).
Tiiy I 21 Scrambler Enable A logic "0" on this input enables the internal scrambler.
Input A logic "I" instructs the chip to bypass the scrambler.
. This output delivers a transmit bit clock generated by chip in
TxCLK o 24 Tfrgrtrl)itggik synchronous mode. When TxSCLK is used, TxCLK is locked on
TxSCLK. This output generates a logic "1" in asynchronous mode.
. This input receives a bit clock sup lied by the DTE. This clock
TxSCLK l 25 "frrg1sp',t,f,igif synchronizes the internal transmit clock of the chip. In line
monitoring mode this input receives the filters clock.
When a logic "O'' is present on this input, the chip delivers on ATO
a modulated signal or a signaling tone and the filtered signal from
iirs l 22 Request to Send EXI. When a logic "1" is present on this input, ATO delivers only
Terminal the filtered signal from EXI. When alogic"-1" is present on this input,
the receive section may be used for line monitoring and ATO
delivers only the filtered signal from EXI.
2/14 Fri" scs-ntomsom
" mmmttsmouues
I: 792923 005.le '35 III
ic,good price


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