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TS68HC901CFN4STN/a4avaiHCMOS MULTI-FUNCTION PERIPHERAL


TS68HC901CFN4 ,HCMOS MULTI-FUNCTION PERIPHERALTS68HC901HCMOS MULTI-FUNCTION PERIPHERALThe TS68HC901 CMFP (CMOS Multi-FunctionPeripheral) is a co ..
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TS68HC901CFN4
HCMOS MULTI-FUNCTION PERIPHERAL
TS68 HC901HCMOS MULTI-FUNCTION PERIPHERAL
The TS68HC901 CMFP (CMOS Multi-Function
Peripheral)isa combinationof manyofthe neces-
sary peripheral functionsina microprocessor sys-
tem.
Includedare:.8 INPUT/OUTPUT PINS Individually programmable direction Individual interrupt source capability Programmable edge selection.16 SOURCE INTERRUPT CONTROLLER8 Internal sources8 External sources Individual source enable Individual source masking Programmable interrupt service modes Polling Vector generation Optional In-service status Daisy chaining capability.FOUR TIMERS WITH INDIVIDUALLY
PROGRAMMABLE PRESCALING Two multimode timers Delay mode Pulse width measurement mode Event counter mode Two delay mode timers Independent clock input Timeout output option.SINGLE CHANNEL USART Full Duplex Asynchronousto65 kbps Byte synchronousto1 Mbps Internal/External baud rate generation DMA handshake signals Modem control Loop back mode.68000 BUS COMPATIBLE
(Ordering Informationattheendofthe Datasheet
DESCRIPTION

The useofthe CMFPina systemcan significantly
reduce chip count, thereby reducing system cost.
The CMFPis completely68000bus compatible,and directly addressable internal registers provide
the necessary control andstatus interfaceto thepro-
grammer.
PDIP48
PLCC52
Figure1: TS68HC901 Block Diagram
INTRODUCTION

The TS68HC901 multi-function peripheral (CMFP)a memberofthe 68000 peripherals. The CMFP
directly interfacestothe 68000 processorviaana-
synchronous bus structure. Both vectored andpol-
led interrupt schemesare supported, withthe CMFP
providing unique vector number generationfor eachits16 interrupt sources. Additio nally, handshake
linesareprovidedto facilitate DMAC interfacing.Re-
ferto block diagramofthe TS68HC901.
The TS68HC901 performs manyof the functions
commonto most microprocessor-based systems.
The resources availabletothe user include:. Eight Individually ProgrammableI/O Pins withIn-
terrupt Capability. 16-Source Interrupt Controller with Individual
Source Enabling and Masking. Four Timers, Twoof whichare Multi-ModeTi-
mers Timers maybe usedas Baud Rate Generators
forthe Serial Channel. Single-Channel Full-Duplex Universal Synchro-
nous/ Asynchronous Receiver-Transmitter(U-
SART) that Supports Asynchronous and withthe
Additionofa Polynomial Generator Checker
Supports Byte Synchronous Formats
Byincorporating multiplefunctions withinthe CMFP,
the system designer retains flexibility while minimi-
zing device count.
Froma programmer’s pointof view,the versatilityof
the CMFP maybe attributedtoits register set. The
registersare well organized and allowthe CMFPto easily tailoredtoa varietyof applications.Allof
the24 registersare also directly addressable which
simplifies programming. The register mapis shown Figure2.
TS68HC901
Address
Abbreviation Register Name
Hex Binary
RS5 RS4 RS3 RS2 RS1

GPIP
AER
DDR
General Purpose I/ORegister
Active Edge Register
Data Direction Register
IERA
IERB
IPRA
IPRB
ISRA
ISRB
IMRA
IMRB
Interrupt Enable RegisterA
Interrupt Enable RegisterB
Interrupt Pending RegisterA
Interrupt Pending RegisterB
Interrupt In-service RegisterA
Interrupt In-service RegisterB
Interrupt Mask RegisterA
Interrupt Mask RegisterB
Vector Register
TACR
TBCR
TCDCR
TADR
TBDR
TCDR
TDDR
TimerA Control Register
TimerB Control Register
TimersCandD Control Register
TimerA Data Register
TimerB Data Register
TimerC Data Register
TimerD Data Register
SCR
UCR
RSR
TSR
UDR
Synchronous Character Register
USART Control Register
Receiver Status Register
Transmitter Status Register
USART Data Register
Note:
Hex addresses assumethatRS1 connectswithA1, RS2connectswithA2, etc...andthatDSis connectedtoLDSon
the 68000orDSis connecttoDSonthe 68008.
Figure2: CMFP Register Map.
TS68HC901
Figure3: PDIPPin connection
PIN DESCRIPTION

GND: Ground
VCC: +5 volts(± 5%)
R/W: Read/Write (input). This input definesa
data transfertasa Read (High)or Write
(Low) cycle. This signalis usedas WR
withan Intel processor type.
DTACK: This output signalsthe completionofthe
operation phaseofa buscycletothe pro-
cessor.Ifthe bus cycleisa processor
read,the CMFP asserts DTACKto indi-
cate thatthe informationonthe Databus valid.Ifthebus cycleisa processorto
the CMFP, DTACK acknowledgesthe
acceptanceofthe databythe CMFP.
DTACKwill beasserted onlybyan CMFP
that hasCSor IAK (and IEI) asserted.
This signalisnot used witha 6800 pro-
cessor type.
Figure4: PLCCPin connection
Pin MOTOROLA

6800 Type
MOTOROLA

Multiplexed
INTEL

R/W
VSS
R/W
ALE: Chip Select (input, active low).CSisu-
sedto selectthe TS68HC901 CMFPfor
accessestothe internal registers.CS
and IACK mustnotbe assertedatthe
same time.: Data Stobe (input, active low).This Input partofthe internal chip select andin-
terrupt acknowledge functions.
The CMFP mustbe locatedonthe lower
portionofthe 16-bit data-busso thatthe
vector number passedtothe processor
duringan interrupt acknowledge cycle
willbe locatedinthelow byteofthe data
word.Asa result,DS mustbe connectedthe processor’s lower data strobeif
vectored interruptaretobe used. Note
thatthis forcesall registerstobe locatedodd addressesand latches dataonthe
rising edgefor writes. This signalis usedRD withan Intel processor type.
TS68HC901
RS1-RS5:
(A1-A5)
Register Address Bus (inputs). Thead-
dress busis usedto address oneofthe
internal registers duringa reador write
cycle.
D0-D7: Data Bus (bi-directional, tri-stateable).
This busis usedto receive data fromor
transmit datatothe MFP’s internal regis-
ters duringa processor reador writecy-
cle. Duringan interrupt acknowledgecy-
cle,the databusis usedto passa vector
numbertothe processor. Sincethe MFPan 8-bit peripheral,the MFP couldbe
locatedon eitherthe upperor lower por-
tionofthe 16-bit data bus (evenor odd
address). However, duringan interrupt
acknowledge cycle,the vector number
passedtothe processor mustbe locatedthelow byteofthe data word.Asare-
sult, D0-D7ofthe MFP mustbe connec-
tedtothelow eightbitsofthe processor
data bus, placing MFP registersat odd
addressesif vectored interruptaretobe
used.
CLK: The clock inputisa single-phase TTL
compatible signal usedfor internalti-
ming. This input shouldnotbe gatedoff any time and must conformto mini-
mum and maximum pulse width times.
The clockisnot necessarilythe system
clockin frequencynor phase. Whenthe
busis multiplexed (MPX=1),an address
strobe signalis connectedtothispin.In
the non multiplexed mode (MPX=0),this
inputis connectedtothe system clock
when used witha 68000 processor typeto VSS (0VDC) when used witha 6800
processor type.
RESET: Device reset. (input, active low). Reset
disablesthe USART receiver and trans-
mitter, stopsall timers and forcestheti-
mer outputs low, disablesall interrupt
channels and clears any pending inter-
rupts. The General Purpose Interrupt/I/O
lineswillbe placedinthe tri-state input
mode.All internal registers (except theti-
mer, USART data registers, and transmit
status register)willbe cleared.
MPX: This input selectsthe databus mode:
MPX=0: non multiplexed mode
MPX=1 :multiplexed mode. Theregister
select lines RS1-RS5 andthe data bus
IRQ: Interrupt Request (output, active low,o-
pen drain). This output signalsthe pro-
cessor thatan interruptis pending from
the CMFP. Theseare16 interrupt chan-
nels that can generatean interruptre-
quest. Clearingthe interrupt pendingre-
gisters (IPRA and IPRB)or clearingthe
interrupt mask registers (IMRA and
IMRB)will cause IRQtobe negated. IRQ
willalsobe negatedas theresultof anin-
terrupt acknowledge cycle, unless addi-
tional interrupts are pendingin the
CMFP. Referto paragraph INTER-
RUPTSfor further information.
IACK: Interrupt Acknowledge (input, active
low). IACKis usedto signalthe
TS68HC901 thatthe CPUis acknow-
ledgingan interrupt.CS and IACk must
notbe assertedatthe same time.
IEI: Interrupt EnableIn (input, active low).IEI usedto signalthe TS68HC901 thatno
higher priority deviceis requesting inter-
rupt service.
IEO: Interrupt EnableOut (output, active low).
IEOis usedto signal lower priority peri-
pherals that neitherthe TS68HC901nor
another higher priority peripheralisre-
questing interrupt service.
I0-I7: General Purpose Interrupt I/O lines.
These lines maybe usedas interruptin-
puts and/orI/O lines. Whenused asinter-
rupt inputs, their active edgeis program-
mable.A data direction register isusedto
define which linesaretobe Hi-Z inputs
and which linesaretobe push-pull TTL
compatible outputs.: Serial Output. Thisisthe outputoftheU-
SART transmitter.: Serial Input. Thisisthe inputtotheU-
SART receiver.: Receiver Clock. This input controlsthe
serialbit rateofthe USARTreceiver.: TransmitterClock. This input controlsthe
serialbit rateofthe USARTtransmitter.: Receiver Ready. (output, active low)
DMA outputfor receiver, which reflects
the statusof Buffer Fullin port number
15.: Transmitter Ready. (output, active low)
DMA outputfor transmitter, whichre-
TS68HC901
TAO,TBO,
TCO,TDO:
Timer Outputs. Eachofthe four timers
hasan output which can producea
square wave. The output will change
states each timer cycle; thus onefullpe-
riodofthe timerout signalis equaltotwo
timer cycles. TAOor TBO canbe reset
(logic ”O”)bya writeto TACR,or TBCR
respectively.
XTAL1,
XTAL2:
Timer Clock inputs.A crystal canbe
connected between XTAL1 and XTAL2, XTAL1 canbe driven witha TTL level
clock. Whendriving XTAL1 with aTTLle-
vel clock, XTAL2 mustbe allowed tofloat.
When usinga crystal,external capacitors
are required. See figure35.All chipac-
cesses are independentof the timer
clock.
TAI,TBI: TimerA,B inputs. These inputs are
control signalsfor timersA andBinthe
pulse width measurement mode ande-
vent count mode. These signals gene-
rate interruptsatthe same priority level
asthe general purpose I/Ointerrupt lines andI3, respectively.I4 andI3donot
haveinterrupt capability whenthe timers
are operatedinthe pulsewidth measure-
ment modeorthe event countmode-un-
der these conditionsI4 andI3 may only usedfor I/O. Referto paragraphTI-
MERSfor further information.
Signal Name Mnemonic I/O Active

Power Input VCC Input High
Ground GND Input Low
Clock CLK Input N/A
Chip Select CS Input Low
Data Strobe DS Input Low
Read/Write R/W Input Read-High/ Write-Low
Data tranfer Acknowledge DTACK Output Low
Register SelectBus RS1-RS5 Input N/A
DataBus D0-D7 I/O N/A
Reset RESET Input Low
Interrupt Request IRQ Output Low
Interrupt Acknowledge IACK Input Low
Interrupt EnableIn IEI Input Low
Interrupt EnableOut IEO Output Low
General PurposeI/O- Interrupt Lines I0-I7 I/O N/A
Timer Clock XTAL1, XTAL2 Input High
Timer Inputs TAI,TBI Input N/A
Timer Outputs TAO, TBO, TCO, TDO Output N/A
Serial Input SI Input N/A
Serial Output SO Output N/A
Receiver Clock RC Input N/A
Transmitter Clock TC Input N/A
Receiver Ready RR Output Low
Transmitter Ready TR Output Low
MPX MPX Input N/A
SIGNAL SUMMARY.
TS68HC901
BUS OPERATION
The followingparagraphs explain thecontrol signals
and bus operation during data transfer operations
and reset.
DATA TRANSFER OPERATIONS.
Transferof data between devices involvesthe follo-
wing pins: Register Select Bus- RS5 through RS1
Data Bus-D0 throughD7 Control Signals Thead-
dressand data busesare separate parallel busesu-
sedto transfer data usingan asynchronous bus
structure.Inall cycles,the bus master assumesre-
sponsibility fordeskewing allsignalsit issuesat both
the start and endofa cycle. Additionally,the bus
masteris responsiblefor deskewingthe acknow-
ledge and data signals fromthe peripheral devices.
Read Cycle.To reada CMFP register,CS andDS
mustbe asserted, and R/W mustbe high. The
CMFPwill placethe contentofthe register whichis
selectedbythe register select bus (RS1 through
RS5)onthe databus(D1 throughD7) and thenas-
sert DTACK. The register addressesare shownon
Figure2. Aftertheprocessorhas latchedthe data,DS negated. The negationof eitherCSorDSwillter-
minate the read operation. The CMFPwill drive
DTACKHighand placeitinthehigh-impedance state.
The timingfora readcycleis shownin figure21.
Write Cycle.To writea registerCSandDS mustbe
asserted,and R/W mustbe low. The CMFPwillde-
code theaddressbusto determine which registeris
selected. Thenthe registerwillbe loaded withthe
contentsofthe data bus and DTACKwillbe asser-
ted. Whenthe processor recognizes DTACK,DS
willbe negated. The write cycleis terminated when
eitherCSorDSis negated. The CMFPwill drive
DTACKhigh andplaceitinthe high-impedance state.
The timingfora write cycleis shownin figure22.
INTERRUPT ACKNOWLEDGE OPERATION.
The CMFP has16 interrupt sources, eight internal
and eight external. Whenan interrupt requestis
pending,the CMFPwill assert IRQ.Ina vectoredin-
terrupt scheme,the processorwill acknowledgethe
interrupt requestby performingan interrupt acknow-
ledge cycle. IACK andDSwillbe asserted. The
CMFPrespondstothe IACK signalby placing avec-
tor numberonthe lower eightbitsofthe data bus.
This vector number correspondstothe IRQ handler
forthe particular interrupt requesting service. The
formatofthis vector numberis givenin figure6.
Whenthe CMFP asserts DTACKto indicatethatva-
lid dataison thebus,the processorwill latchtheda- and terminate the bus cycleby negating DS.
When eitherDSor IACKare negated,the CMFPwill
terminate the interrupt acknowledge operationby
driving DTACK high and placingitinthe high-impe-
dance state. Also,the databuswillbe placedinthe
high-impedance state. IRQwillbe negatedasare-
sultofthe IACK cycle unless additional interrupts
are pending.
The CMFP canbe partofa daisy-chain interrupt
structure which allows multiple CMFPstobe placedthe same interrupt levelby sharinga common
IACK signal.A daisy-chain priority schemeis imple-
mented withIEI and IEO signals.IEI indicates that higher priority deviceis requesting interrupt ser-
vice. IEO signals lower priority devices that neither
this devicenorany higher priority devicesis reques-
ting service.To daisy-chain CMFPs,the highest
priority CMFP hasitsIEI tied low and successive
CMFPs have theirIEI connectedtothe next higher
priority device’s IEO. Notethatwhenthe daisy-chain
TS68HC901
interrupt structureisnot implemented,theIEIofall
CMFPs mustbe tied low.
Whenthe processor initiatesan interrupt acknow-
ledge cycleby driving IACK and DS, the CMFP
whoseIEIislow may respond witha vector number interruptis pending.Ifthis device doesnot havea
pending interrupt, IEOis asserted which allowsthe
next lower priority deviceto respondtothe interrupt
acknowledge. Whenan CMFP propagates IEO,it
willnot drivethe databusnor DTACK duringthein-
terrupt acknowledge cycle. The timingforan IACK
cycleis shownin figure23 and24.
RESET OPERATION
The reset operation will initialize the CMFPtoa
known state. The reset operation requires thatthe
RESET inputbe assertedfora minimumof two
microseconds. Duringa device reset condition,all
internal CMFP registersare cleared exceptforthe
timer data registers (TADR, TBDR, TCDR and
TDDR),the USART data register (UDR),the trans-
mitter status register (TSR) andthe interrupt vector
register.All timersare stopped andthe USARTre-
ceiver and transmitterare disabled. The interrupt
channelsare also disabled and any pending inter-
ruptsare cleared.In addition,the general purpose
interruptI/O linesare placedinthe high- impedance
input mode andthe timer outputs aredriven low.Ex-
ternalCMFP signals arenegated. Theinterrupt vec-
tor registeris initializedtoa 0Fh.
NON MULTIPLEXED MODEthis mode,the MPX inputmustbe setto zero,and
the TS68HC901canbe used witha 68000 proces-
sortypeora 6800 processor type. Referto figure2124forthe electrical characteristics.
Witha 6800 processor typetheDSpinis connectedtheE signalofthe processor,the DTACK signalnot usedandthe CLK mustbe zeroed.
MULTIPLEXED MODE
The CMFPcanbe used eitherona MOTOROLAor
INTELbus type. Inthis casethe MPX pinisconnec-
tedto Vcc. The table page4 givesthe significationthe different signals used.A dummy accesstothe
TS68HC901 hastobe done before anyvalidaccess ordertosetupthe internal logicof sampling.
TS68HC901
INTERRUPT STRUCTUREa 68000 system,the CMFPwillbe assignedto
oneofthe seven possible interrupt levels.All inter-
rupt service requests fromthe CMFP’s16 interrupt
channels willbe presentedatthis level. Although,as interrupt controller,the CMFPwill internally prio-
ritizeits16 interrupt sources. Additional interrupt
sources maybe placedatthe same interrupt level daisy-chaining multiple CMFPs. The CMFPswill prioritizedby their positioninthe chain.
INTERRUPT PROCESSING
Each CMFP provides individual interrupt capability
forits various functions. Whenan interruptis recei-
vedonone ofthe external interrupt channelsor from
oneofthe eight internal sources,the CMFPwillre-
quest interrupt service. The16 interrupt channels
areassigneda fixed prioritysothat multiple pending
interruptsare servicedaccordingto their relativeim-
portance. Sincethe CMFP can internally generate vectornumbers,the unique vector number which
correspondstothe highest priority channel thatas pending interrupt ispresentedto theprocessordu-
ringan interrupt acknowledge cycle. This unique
vector number allowsthe processorto immediately
begin executionofthe interrupt handlerforthe inter-
rupt source, decreasing interrupt latency time.
INTERRUPT CHANNEL PRIORITIZATION
The16 interrupt channelsare prioritizedas shown figure5. General purpose interrupt7(I7)isthehi-
ghest priority interrupt channel andI0isthe lowest
priority channel. Pending interrupts arepresentedto
the CPUin orderof priority unless they have been
maskedoff.By selectively masking interrupts,the
channelarein effect re-prioritized.
INTERRUPT VECTOR NUMBER FORMAT
Duringan interrupt acknowledge cycle,a unique8-
bit vector numberis presentedtothe system which
correspondstothe specific interrupt source whichis
requesting service. The formatof the vectoris
shownin figure6. The most significant fourbitsof
the interrupt vectornumberare userprogrammable.
These bitsaresetby writingthe upper fourbitsof
the vector register whichis shownin figure7. The
low order bits are generated internallyby the
TS68HC901. Note thatthe binary channel number
shownin figure5 correspondstothelow orderbitsthe vector number associated with each channel.
Figure9
: Interrupt Channel Prioritization
Priority Channel Description

HIGHEST
LOWEST
General Purpose Interrupt 7(I7)
General Purpose Interrupt 6(I6)
TimerA
Receive BufferFull
Receive Error
Transmit Buffer Empty
Transmit Error
TimerB
General Purpose Interrupt 5(I5)
General Purpose Interrupt 4(I4)
TimerC
TimerD
General Purpose Interrupt 3(I3)
General Purpose Interrupt 2(I2)
General Purpose Interrupt 1(I1)
General Purpose Interrupt 0(I0)
Figure5: Interrupt Channel Prioritization
TS68HC901
V6 V5 V4 IV3 IV2 IV1 IV0V7-V4 The fourmost significantbitsare copied fromthe register
IV3-IV0 Thesebitsare suppliedbythe CMFP. Theyarethe binary channel numberofthe highest
priority channel thatis requesting interrupt service.
Figure6:
VECTOR REGISTER 0
(17h) V7 V6 V5 V4 S 0* 0* 0*
Writing0: CLEARED
Writing1: SET
CLEAREDon RESET
V7-V4 The upper fourbitsofthe vector registerare writtenbythe user. Thesebits become themost
significant fourbitsofthe interrupt vector number. In-Service Register Enable. WhentheSbitis zero,the CMFP isinthe automatic end-of-in-
terrupt mode andthe In-Service register bitsare forced low. WhentheSbitisa one,the
CMFPisinthe software end-of-interrupt mode andthe In-Service registerbitsare enabled. Unused bits, readas zero.
Figure7:
TS68HC901 TS68HC901 TS68HC901
Figure8: Daisy Chaining
TS68HC901
DAISY-CHAINING CMFPsan interrupt controller,the TS68HC901 CMFP
will support eight external interrupt sourcesin addi-
tiontoits eight internal interrupt sources. Whena
system requires more than eight external interrupt
sourcestobe placedatthe same interrupt level,
sources maybe addedto theprioritized structureby
daisy-chaining CMFPs. Interrupt sourcesare priori-
tized internally within each CMFP andthe CMFPs
are prioritizedby their positioninthe chain. Unique
vector numbers are providedfor each interrupt
sources.
TheIEI and IEO signals implementthe daisy-chai-
nedinterrupt structure. TheIEIofthe highest priority
CMFPis tiedlow andthe IEO outputof this device tiedtothe next highest priority CMFP’sIEI. The
IEIand IEOsignalsaredaisy-chained inthis manner
forall CMFPsinthe chain, withthe lowest priority
CMFP’s IEOleft unconnected.A diagramofanin-
terrupt daisy-chainis shownin figure8.
Daisy-chaining requires thatall partsinthe chain
havea common IACK. Whenthe common IACKis
asserted duringan interrupt acknowledge cycle,all
partswill prioritize interruptsin parallel. WhentheIEI
signaltoa CMFPis asserted,the part may respond the IACK cycleifit requires interrupt service.
Otherwise,the partwill assert IEOtothe next lower
priority device. Thus, priorityis passed downthe
chainviaIEI and IEO untila part whichhas appen-
ding interruptis reached. The part withthe pending
interrupt passesa vector numbertothe processor
and doesnot propagate IEO.
Figure9a:
Figure9b:
TS68HC901
INTERRUPT CONTROL REGISTERS
CMPF interrupt processingis managedbythe inter-
rupt enable registersA andB, interrupt pendingre-
gistersA andB, and interrupt mask registersAand These registers allowthe programmerto enable disable individual interrupt channels, mask indi-
vidual interrupt channels, and accesspending inter-
rupt status information. In-service registersAandB
allow interruptstobe nested asdescribed hereafter.
The interrupt control registers are shownin fig-
ure10.
INTERRUPT ENABLE REGISTERS
The interrupt channelsare individually enabledordi-
sabledby writinga oneor zero, respectively,tothe
appropriatebitof interrupt enable registerA (IERA) interrupt enable registerB (IERB). The processor
may read these registersat anytime.
Whena channelis enabled, interrupts receivedon
the channelwillbe recognizedbythe CMFP and
IRQwillbe assertedtothe processor, indicating that
interrupt serviceis required.Onthe other hand,adi-
sabled channelis completely inactive; interruptsre-
ceivedonthe channelare ignoredbythe CMFP.
Writinga zerotoabitof interrupt enable registerABwill causethe correspondingbitof interrupt pen-
ding registerAorBtobe cleared. This willterminate
all interrupt service requestsforthe channel andal- negate IRQ, unless interruptsare pending from
other sources. Disablinga channel, however, does
not affectthe correspondingbitin interrupt in-ser-
vice registersAorB.So,ifthe CMFPisinthe soft-
ware end-of-interrupt mode andan interruptisin
service whena channelwill remainset until cleared software.
INTERRUPT PENDING REGISTERS
Whenan interruptis receivedonan enabled chan-
nel,the corresponding interrupt pendingbitissetin
interrupt pending registerAorB (IPRAor IPRB).In vectored interrupt scheme,thisbitwillbe cleared
whenthe processor acknowledgesthe interrupting
channel andthe CMFP responds witha vector num-
ber.Ina polled interrupt system,the interrupt pen-
ding registers mustbe readto determinethe inter-
rupting channel and thenthe interrupting pendingbit clearedbythe interrupt handling routine without
performingan interrupt acknowledge sequence. singlebitofthe interrupt pending registersis clea-
redin softwareby writing onestoallbit positionsex-
ceptthebittobe cleared. Note that writing onesto
IPRA and IPRB hasno effectonthe contentsofthe
register.A singlebitofthe interrupt pending regis-
ters isalso cleared when thecorresponding channel disabledby writinga zerotothe appropriatebitof
IERAor IERB.
INTERRUPT MASK REGISTERS
Interruptsare maskedfora channelby clearingthe
appropriatebitin interrupt mask registerAorB (IM-or IMRB). Even thoughan enabled channelis
masked,the channelwill recognize subsequentin-
terrupts andsetits interrupt pendingbit. However,
the channelis prevented from requesting interrupt
service (IRQtothe processor)as longasthe mask
bitforthat channelis cleared. achannelis requesting interrupt serviceat thetime
thatits correspondingbitin IMRAor IMRBis clea-
red,the requestwill ceaseand IRQwillbe negated,
unless another channelis requesting interrupt ser-
vice. Later, whenthe maskbit isset, anypendingin-
terruptonthe channelwillbe processed accordingthe channel’s assigned priority. IMRA and IMRB
maybe readat any time.
TS68HC901
INTERRUPT ENABLE REGISTERS 0IERA
(07h) GPIP7 GPIP6 TIMERA RCV
Bufferfull
RCV
Error
XMIT
Buffer Empty
XMIT
Error TIMERB
IERB
(09h) GPIP5 GPIP4 TIMERC TIMERD GPIP3 GPIP2 GPIP1 GPIP0 INTERRUPT PENDING REGISTERS 0
IPRA
(0Bh) GPIP7 GPIP6 TIMERA RCV
Bufferfull
RCV
Error
XMIT
Buffer Empty
XMIT
Error TIMERB
IPRB
(0Dh) GPIP5 GPIP4 TIMERC TIMERD GPIP3 GPIP2 GPIP1 GPIP0
Writing0: CLEAR
Writing1: UNCHANGED INTERRUPT IN-SERVICE REGISTERS 0
ISRA
(0Fh) GPIP7 GPIP6 TIMERA RCV
Bufferfull
RCV
Error
XMIT
Buffer Empty
XMIT
Error TIMERB
ISRB
(11h) GPIP5 GPIP4 TIMERC TIMERD GPIP3 GPIP2 GPIP1 GPIP0 INTERRUPT MASK REGISTERS 0
IMRA
(13h) GPIP7 GPIP6 TIMERA RCV
Bufferfull
RCV
Error
XMIT
Buffer Empty
XMIT
Error TIMERB
IMRB
(15h) GPIP5 GPIP4 TIMERC TIMERD GPIP3 GPIP2 GPIP1 GPIP0
Writing0: MASKED
Writing1: UNMASKED
Figure10:
TS68HC901
NESTING CMFPINTERRUPTSa 68000 vectored interrupt system,the CMFPis
assignedto oneof seven possible interrupt levels.
Whenan interruptis received from theCMFP,anin-
terrupt acknowledgefor that levelis initiated. Once interruptis recognizedata particular level, inter-
ruptsat that same levelor beloware maskedby
68000.As longasthe processor’s interrupt maskis
unchanged,the 68000 interrupt structurewill prohi-
bitthe nestingof interruptsatthe same interruptle-
vel. However, additional interrupt requests fromthe
CMFP canbe recognized beforea previous chan-
nel’s interrupt service routineis completedby lowe-
ringthe processor’s interrupt maskto thenext lower
interrupt level withinthe interrupt handler.
When nesting CMFP interrupts,it maybe desirable permit interruptson any CMFP channel, regar-
dlessofits priority,to preemptor delay interrupt pro-
cessingofan earlier channel’s interrupt servicere-
quest.Or,it maybe desirableto only allow sub-
sequent higher priority channel interrupt requeststo
supersede previously recognized lower priorityin-
terrupt requests. The CMFP interrupt structure pro-
vides this flexibilityby offering two end-of-interrupt
optionsfor vectored interrupt schemes. Note that
the end-of-interrupt modesarenot activeina polled
interrupt scheme.
SELECTING THE END-OF-INTERRUPT MODEa vectored interrupt scheme,the CMFP maybe
programmedto operatein eitherthe automatic end-
of-interrupt modeorthe software end-of-interrupt
mode. The modeis selectedby writingtheSbitof
the vector register (see figure7). WhentheSbitis
programmedtoa one,the CMFPis placedinthe
software end-of-interrupt mode and whentheSbita zero,all channels operateinthe automatic end-
of-interrupt mode.
AUTOMATIC END-OF-INTERRUPT
Whenan interrupt vector numberis passedtothe
processor duringan interrupt acknowledge cycle,
the corresponding channel’s interrupt pendingbitis
cleared.Inthe automatic end-of-interrupt mode,no
further historyofthe interrupt remainsinthe CMFP.
The in-servicebitsofthe interrupt in-service regis-
ters (ISRA and ISRB)are forced low. Subsequent
interrupts whichare receivedon anyCMFP channel
will generatean interrupt requesttothe processor,
evenifthe currentinterrupt’s service routine hasnot
been completed.
SOFTWARE END-OF-INTERRUPTthe software end-of-interrupt mode,the channel’s
associated interrupt pendingbitis cleared and inad-
dition,the channel’s in-servicebitof in-service regis-
terAorBisset whenits vector numberis passedthe processor during anIACKcycle.A higher prio-
rity channel maysubsequently request interrupt ser-
viceandbe acknowledged,butas longasthe chan-
nel’s in-servicebitis set,no lower priority channel
may request interrupt servicenor passits vectordu-
ringan interrupt acknowledge sequence.
While only higher priority channels may requestin-
terrupt service,any channel can receivean interrupt
andsetits interrupt pendingbit. Eventhe channel
whose in-servicebitis setcan receivea secondin-
terrupt. However,no interrupt service requestis
made untilits in-servicebitis cleared.
The in-servicebitfora particular channel canbe
clearedby writinga zerotoits correspondingbitin
ISRAor ISRB and onestoall otherbit positions.
Since bitsinthe in-service registers can onlybe
clearedin software andnot set, writing onestothe
register does not alter their contents. ISRA and
ISRB maybe readatany time.
TS68HC901
GENERAL PURPOSE INPUT/OUTPUT
INTERRUPT PORT

The general purpose interrupt input/output (I/O) port
(GPIP) provides eightI/O lines(I0 throughI7) that
maybe operatedas either inputsor outputs under
software control.In addition, these lines may optio-
nally generatean interrupton eithera positive trans-
itionor negative transitionofthe input signal. The
flexibilityof theGPIP allowsitto beconfiguredasan
8-BitI/0 portorforbit I/O. Since interruptsareen-
abledona bit-by-bit basis,a subsetofthe GPIP
couldbe programmedas handshake linesorthe
port couldbe connectedtoas manyas eight exter-
nal interrupt sources, which wouldbe prioritizedby
the CMFP interrupt controllerfor interrupt service.
6800 INTERRUPT CONTROLLER
The CMFP interrupt controlleris particularly usefula system whichhas many 6800-type devices.Ty-
pically,ina vectored 68000 system, 6800-typepe-
ripherals usethe autovector which correspondsto
their assigned interrupt level since theydonot pro-
videa vector numberin responsetoanAC cycle.
The autovector interrupt handler must then pollall
6800-type devicesat that interrupt levelto deter-
mine which deviceis requesting service. However, tyingthe IRQ output froma 6800-type deviceto
the general purposeI/O interrupt port (GPIP)ofa
CMFP,a unique vector numberwillbe providedto
the processor duringan interrupt acknowledgecy-
cle. This interrupt structurewill significantly reduce
interrupt latencyfor6800-type devices andotherpe-
ripheral devices whichdonot support vector-by-de-
vice.
GPIP CONTROL REGISTERS
The GPIPis programmedvia threecontrol registers
shownin figure 11.These registers controlthe data
direction provide user accessto theport, andspecify
the active edgefor eachbitofthe GPIP whichwill
producean interrupt. These registersare described detailinthe following paragraphs.
GPIP DATA REGISTER
The general purposeI/O data registeris usedtoin-
putor output datatothe port. When datais writtenthe GPIP data register, those pins whicharede-
finedas inputswill remaininthe high-impedance
state. Pins which aredefined asoutputswill assume
the state (highor low)of their correspondingbitin
the data register. Whenthe GPIPis read, datawill passeddirectly fromthebitsof thedata register
for pins whichare defined asoutputs. Datafrom pins
definedas inputswill come fromthe input buffers.
ACTIVE EDGE REGISTER
The active edge register (AER) allows eachofthe
GPIP linesto producean interrupton eithera one-
to-zeroora zero-to-one transition. Writing azerothe
appropriate edgebitofthe active edge register
causesthe associated inputto generatean interruptthe one-to-zero transition. Writinga onetothe
edgebitwill producean interrupt onthe zero-to-one
transitionofthe corresponding GPIP line.
TS68HC901
ACTIVE EDGE REGISTER 0AER
(03h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 1= RISING= FALLING
DATA DIRECTION REGISTER
DDR
(05h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 1= OUTPUT= INPUT
GENERAL PURPOSEI/O DATA REGISTER
GPIP
(01h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0
Figure11:
Note

The transition detectorisan exclusive-OR gate
whose inputsarethe edgebit andthe input buffer.a result, writingthe EAR may causean interrupt-
producing transition, depending uponthe stateof
the input.So,the AER shouldbe configured before
enabling interruptsviathe interrupt enable registers
(IERAand IERB). Also, changingthe edgebit while
interrupts areenabled maycausean interruptonthe
corresponding channel.
DATA DIRECTION REGISTER
The data direction register (DDR) allowsthe pro-
grammerto defineI0 throughI7as inputs oroutputs writingthe correspondingbit. Whenabitofthe
data direction registeris writtenasa zero,the cor-
responding interruptI/Opinwillbea high-impe-
dance input. Writinga oneto anybitofthe datadi-
rection registerwill causethe correspondingpinto configuredasa push-pull output.
TS68HC901
TIMERS
The CMFP contains four 8-bit timers which provide
manyfunctions typically requiredin microprocessor
systems.The timerscan supply thebaud rate clocks
forthe on-chip serialI/O channel, generate periodic
interrupts, measure elapsed time, and count signal
transitions.In addition, two timers have waveform
generation capability.
All timers are prescaler/counter timers witha
common independent clock input (XTAL1or
XTAL2) andare notrequiredto beoperated fromthe
system clock. Each timer’s output signal toggles
whenthe timer’s main counter timesout. Additional-
ly, timersA andB have auxiliary control signals
whichare usedin twoofthe operation modes.An
interrupt channelis assignedto each timer and
whenthe auxiliary control signalsare used,a sepa-
rate interrupt channelwill respondto transitionson
these inputs.
OPERATION MODES
TimersA andBarefull function timers which,inad-
ditiontothe delay mode, operateinthe pulse width
measurement mode andthe event count mode.Ti-
mersC andDare delay timers only.A brief discus-
sionof eachofthe timer modes follows.
DELAY MODE OPERATION
All timers may operateinthe delay mode.In this
mode,the prescaleris always active. The prescaler
specifiesthe numberof timer clock cycles which
must elapse beforea count pulseis appliedtothe
main counter.A count pulse causesthe main coun-
terto decrementby one. Whenthe timerhas decre-
mented downto01 (hexadecimal),the next count
pulsewill causethe main countertobe reloaded
fromthe timer data registeranda timeout pulsewill produced. This timeout pulseis coupledtothe
timer’s interrupt channel and,ifthe channelisen-
abled, aninterrupt willoccur. The timeout pulse also
causesthe timeroutputpinto toggle. The outputwill
remaininthis new state untilthe next timeout pulse
occurs.
For example, ifdelay modewithadivide-by-10 pres-
caleris selectedand thetimerdataregister isloaded
with 100 (decimal),the main counterwill decrement
once every10 timer clock cycles. After 1,000 timer
clocks,a timeout pulsewillbe produced. This time
out pulsewill generatean interruptifthe channelis
enabled (IERA, IERB) andin addition,the timer’s
outputlinewill toggle. The outputlinewill complete
onefull period every 2,000 cyclesofthe timer clock.the prescaler valueis changed whilethe timeris
enabled,the first timeout pulsewill occuratanin-
determinate timeno less than onenor more than
200 timer clock cycles. Subsequent timeout pulses
will then occuratthe correct interval.the main counteris loaded with01 (hexadecimal), timeout pulsewill occur every timethe prescaler
presentsa count pulsetothe main counter.Ifthe
main counteris loaded with00,a timeout pulsewill
occur every 256 count pulses.
PULSE WIDTH MEASUREMENT OPERATION
Besidesthe delay mode, timersAand Bmaybe pro-
grammedto operateinthe pulse width measure-
ment mode.In this modean auxiliary control input required; timersA andB auxiliary input linesare
TAI and TBI. Also,inthe pulse width measurement
mode, interrupt channels normally associated with andI3will respond totransitionsonTAI and TBI,
respectively. General purpose linesI3 andI4 may
stillbe usedforI/O.A conceptual circuitofthe timers
TS68HC901
the pulse width measurement modeis showninFigure12.
The pulse width measurement mode functions simi-
larlytothe delay mode, withthe auxiliary controlsi-
gnal actingasan enabletothe timer. Whenthe
control signalis active, theprescalerand main coun-
terare allowedto operate. Whenthe control signal negated,the timeris stopped.So,the widthofthe
active pulseonTAIorTBIis measuredbythe num-
berof timer counts which occur whilethe timerisal-
lowedto operate.
The active stateofthe auxiliary input lineis definedthe associated interrupt channel’s edgebitinthe
active edge register (AER). GPIP4of theAERisthe
edgebit associated withTAIand GPIP3is associa-
ted with TBI. Whenthe edgebitisa one, theauxiliary
inputwillbe active high, enablingthe timer whilethe
input signalisata high level.Ifthe edgebitis low,
the auxiliary inputwillbe activelow andthetimerwill
operate whilethe input signalisatalow level.
The stateofthe active edgebit also specifies whe-
thera zero-to-one transitionora one-to-zero trans-
ition ofthe auxiliary inputpin willproducean interrupt
whenthe interrupt channelis enabled.In normalo-
peration, programmingthe active edgebittoa one
will producean interruptonthe zero-to-one trans-
itionofthe associated input signal. Alternately, pro-
grammingthe edgebittoa zerowill produceanin-
terruptonthe one-to-zero transitionofthe inputsi-
gnal. However,in the pulse width measurement
mode,the interrupt generatedbya transitiononTAITBIwill occuronthe opposite transitionas that
normally definedbythe edgebit.
For example,in the pulse width measurement
mode,ifthe edgebitisa one,the timerwillbe allo-
wed torunwhilethe auxiliary input TAIis high. When
TAI transitions from highto low,the timerwill stop
and,ifthe interrupt channelis enabled,an interrupt
will occur.By havingthe interrupt occuronthe one-
to-zero transition insteadofthe zero-to-one trans-
ition,the processor willbe interrupted when the
pulse being measuredhas terminatedandthe widththe pulseis available fromthe timer. Therefore,
the timersactlikea divide-by-prescaler that canbe
programmedbythe timer data register andtheti-
mer’sA andB control register.
After readingthe contentsofthe timer,the main
counter mustbe reinitializedby writingtothe timer
data registerto allow consecutive pulsestobe mea-
sured.Ifthe timeris written afterthe auxiliary input
signalis active, thetimerwill count fromthe previous
contentsofthe timer data register untilit counts
through01 (hexadecimal).Atthe time,the main
counteris loaded withthe value fromthe timer data
Figure12:
TS68HC901
glethe timer output, and aninterrupt maybe optio-
nally generatedonthe timer interrupt channel.
Note thatthe pulse width measuredwill include
counts from beforethe main counter was reloaded.the timer data registeris written whilethe pulseis
transitioningtothe active state,an indeterminateva-
lue maybe written intothe main counter.
Oncethe timeris reprogrammedfor another mode,
interruptswill again occurasnormally definedbythe
edgebit. Note that aninterrupt maybe generatedas
the resultof placingthe timer intothe pulse width
measurement modeorby reprogrammingthe timer
for another mode. Also,an interrupt maybe gene-
ratedby changingthe stateofthe edgebit whilein
the pulse width measurement mode.
EVENT COUNT MODE OPERATION additiontothe delay mode andthe pulse width
measurement mode, timersA andB maybe pro-
grammedto operateinthe event count mode. Like
the pulse width measurement mode, the event
count mode also requiresan auxiliary input signal,
TAIor TBI, andthe interrupt channels normallyas-
sociated withI4andI3will respondto transitionson
TAI andTBI respectively. General purpose linesI3
andI4 only functionasI/O ports.the event count modethe prescaleris disabled,
allowing each active transitionon TAIand TBItopro-
ducea count pulse. The count pulse causesthe
main counterto decrementby one. Whenthe timer
counts through01 (hexadecimal),a timeout pulse generated whichwill causethe output signalto
toggle and may optionally producean interruptvia
the associated timer interrupt channel. The timer’s
main counter isalsoreloaded from thetimer datare-
gister.To count transitions reliably,the input signal
may only transition once every four timer clockpe-
riods.For this reason,the input signal must havea
maximum frequency equalto one-fourth thatofthe
timer clock.
The active edgeofthe auxiliary input signalis defi-
nedbythe associated interrupt channel’s edgebit.
GPIP4ofthe AER specifiesthe active edgeforTAI
and GPIP3 definesthe active edgefor TBI. When
the edgebitis progra mmedtoa one,a count pulse
willbe generatedonthe zero-to-one transitionofthe
auxiliary input signal. Whenthe edgebitis program-
medtoa zero,a count pulsewillbe generatedon
the one-to-zero transition. Also, note that changing
the stateofthe edgebit whilethe timerisin theevent
count mode may producea count pulse.
Besides generatinga count pulse,the active trans-
itionofthe auxiliary input signalwill also producean
interruptontheI3orI4 interrupt channel,ifthein-
terrupt channelis enabled. Typically,inthe event
count mode, these channelsarenot enabled since
the timeris automatically counting transitionsonthe
input signal.Ifthe interrupt channelis enabled,the
numberof transitions couldbe countedinthe inter-
rupt routine without requiringthe useofthe timer.
TIMER REGISTERS
The fourtimersare programmedvia three controlre-
gisters and four timer data registers. Control regis-
ters TACR and TBCR and timer data registers
TADRand TBDR (referto figure 5.1) areassociated
with timersAandB respectively. TimersC andDare
controlledbythe control register TCDCR andthe
data registers TCDRand TDDR (referto Figure13).
TIMER DATA REGISTERS
Each timer’s main counterisan 8-bit binary down
counter. Thevalueofthe main counter maybe read anytimeby reading thetimer’s data register. The
information readisthe valueofthe counter which
was capturedonthelast low-to-high transitionofthe pin.
The main counteris initializedby writingtotheti-
mer’s data register.Ifthe timeris stopped, datais
loadedsimultaneouslyintoboth thetimerdata regis-
ter andthe main counter.Ifthe timer data register written whilethe timeris enabled,the valueisnot
loadedintothe timer untilthe timer counts through (hexadecimal). Writing the timer data register
whilethe timeris counting through01(hexadecimal)
will causean indeterminate valuetobe loaded into
the timer’smain counter. The four data registersare
shownin Figure13.
TIMER CONTROL REGISTERS
Bitsinthe timercontrol registers selectthe operation
mode, selectthe prescaler value,and disable theti-
mers. Timer control registers TACRand TBCR also
havebits which allowthe programmerto reset out-
TS68HC901
(a) TIMERA DATA REGISTER 0TADR
(1Fh) D7 D6 D5 D4 D3 D2 D1 D0
(b) TIMERB DATA REGISTER
TBDR
(21h) D7 D6 D5 D4 D3 D2 D1 D0
(c) TIMERC DATA REGISTER
TCDR
(23h) D7 D6 D5 D4 D3 D2 D1 D0
(d) TIMERD DATA REGISTER
TDDR
(25h) D7 D6 D5 D4 D3 D2 D1 D0
CLEAREDon RESET Writing0: CLEARED
Writing1: SET
Figure13:
TS68HC901
TIMERA CONTROL REGISTER 0TACR
(19h) 0* 0* 0* TA0
RESET AC3 AC2 AC1 AC0
TIMERB CONTROL REGISTER
TBCR
(1Bh) 0* 0* 0* TB0
RESET BC3 BC2 BC1 BC0
CLEAREDon RESET Unused bits, readas zero.
RESET
TA0/TB0
Timer’sA andB output lines (TA0 and TB0) maybe forcedlowat any timeby writinga onethe reset locationin TACR and TBCR, respectively. The outputwillbe heldlow only during
the write operation;at theconclusionofthe operationthe outputwillbe allowedto togglein
responsetoa time-out pulse. When resetting TA0 and TB0,the remainingbits inthe control
register mustbe written with their previous valueto avoid alteringthe operation mode.
SET:Endof write cycle which clearsthebit
CLEARED:MPUwritesa zero
AC3-AC0
BC3-BC0
Thesebitsare decodedto determinethe timer operation mode.
AC3
BC3
AC2
BC2
AC1
BC1
AC0
BC0 Operation Mode

Timer Stopped*
Delay Mode,÷4 Prescaler
Delay Mode,÷10 Prescaler
Delay Mode,÷16 Prescaler
Delay Mode,÷50 Prescaler
Delay Mode,÷64 Prescaler
Delay Mode,÷100 Prescaler
Delay Mode,÷200 Prescaler
Event Count Mode
Pulse Width Mode,÷4 Prescaler
Pulse Width Mode,÷10 Prescaler
Pulse Width Mode,÷16 Prescaler
Pulse Width Mode,÷50 Prescaler
Pulse Width Mode,÷64 Prescaler
Pulse Width Mode,÷100 Prescaler
Pulse Width Mode,÷200 Prescaler Regardlessofthe operation mode, countingis inhibited whenthe timeris stopped.The
contentsofthe timer’s main counterisnot affected, althoughany residual countinthe
prescaleris lost.
SET:Endof write cycle which clearsthebit
CLEARED: MPUwritesa zero
Figure14:
TS68HC901
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