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TPS51206DSQR
2A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference for DDR2, DDR3, DDR3L
VTT
VTTSNS
PGND
VTTREF
VDDQSNS
VLDOIN
TPS51206 VDDGND
PowerPad
VTT
VTTREFS3_SLP
S5_SLP
5 V or 3.3 V
Supply
VDDQ
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TPS51206SLUSAH1C –MAY 2011–REVISED AUGUST 2016
TPS51206 2-A Peak Sink/ Source DDR Termination Regulator With VTTREF Buffered
Reference for DDR2, DDR3, DDR3L, and DDR4 Features Supply Input Voltage: Supports 3.3-V Rail and 5-V
Rail VLDOIN Input Voltage Range: VTT+0.4Vto 3.5V VTT Termination Regulator Output Voltage Range: 0.5Vto 0.9V 2-A Peak Sink and Source Current Requires Only 10-μF MLCC Output Capacitor ±20 mV Accuracy VTTREF Buffered Reference VDDQ/2± 1% Accuracy 10-mA Sink and Source Current Supports High-Zin S3 and Soft-Stopin S4 and S5
with S3 and S5 Inputs Overtemperature Protection 10-Pin,2 mm×2 mm SON (DSQ) Package
Applications DDR2, DDR3, DDR3L, and DDR4 Memory Power
Supplies SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination
DescriptionThe TPS51206isa sink and source double date rate
(DDR) termination regulator with VTTREF buffered
reference output.Itis specifically designed for low-
input voltage, low-cost, low-external component count
systems where spaceisa key consideration. The
TPS51206 maintains fast transient response and only
requires1× 10-µFof ceramic output capacitance.
The TPS51206 supportsa remote sensing function
and all power requirements for DDR2, DDR3 and
Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The
VTT current capabilityis ±2-A peak. The device
supportsallof the DDR power states, putting VTTto
High-Zin S3 state (suspendto RAM) and discharging
VTT and VTTREFin S4 or S5 state (suspendto
disk).
The TPS51206is availablein 10-pin,2×2, SON
(DSQ) PowerPAD™ package and specified from
–40°Cto 85°C.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe datasheet.
Simplified Application
