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TPIC6259TIN/a18avai8-Bit Addressable Latch
TPIC6259DWTI N/a10avai8-Bit Addressable Latch
TPIC6259DWRTIBBN/a200avai8-Bit Addressable Latch
TPIC6259DWRG4TIN/a2530avai8-Bit Addressable Latch 20-SOIC
TPIC6259NTIN/a83avai8-Bit Addressable Latch


TPIC6259DWRG4 ,8-Bit Addressable Latch 20-SOIC maximum ratings over the recommended operating case temperature range (unless†otherwise noted)Logic ..
TPIC6259N ,8-Bit Addressable Latchlogic diagram (positive logic)4DRAIN03S0D C1CLR5DRAIN1D C1CLR6DRAIN2D C18S1CLR7DRAIN3D ..
TPIC6273 ,Octal D-type Latchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
TPIC6273DW ,Octal D-type Latchmaximum ratings over recommended operating case temperature range (unless†otherwise noted)Logic sup ..
TPIC6273DWRG4 ,Octal D-type Latch 20-SOIC features an open-drain power 3 5D2 DRAIN2DMOS transistor output.8 6D3 DRAIN39 7When clear (CLR) is ..
TPIC6273N ,Octal D-type Latch TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995• Low r . . . ..
TS3USB221ARSER ,High-Speed USB 2.0 1:2 Mux/Demux Switch With Single Enable and ESD Protection 10-UQFN -40 to 85Features 3 DescriptionThe TS3USB221A device is a high-bandwidth switch1• V Operation at 2.5 V to 3. ..
TS3USB221DRCR ,High-Speed USB 2.0 (480 Mbps) 1:2 Multiplexer/Demultiplexer Switch With Single Enable 10-VSON -40 to 85Features FROM: V Operation at 2.5 V and 3.3 V TO: V Operation at 2.3 V and 3.6 V....... 1CC CC• Add ..
TS3USB221ERSER ,High-Speed USB 2.0 (480-Mbps) 1:2 Multiplexer/Demultiplexer Switch With Single Enable 10-UQFN -40 to 85Features 3 DescriptionThe TS3USB221E is a high-bandwidth switch1• V Operation of 2.5 V to 3.3 VCCsp ..
TS3USB221RSER ,High-Speed USB 2.0 (480 Mbps) 1:2 Multiplexer/Demultiplexer Switch With Single Enable 10-UQFN -40 to 85Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV – ..
TS3USB3000RSER ,DPDT USB 2.0 High-Speed and Mobile High-Definition Link (MHL) (6.1GHz) Switch 10-UQFN -40 to 85Features:isolation of the signal lines under such conditionwithout excessive leakage current. The s ..
TS3USB30EDGSR ,High-Speed USB 2.0 1:2 Mux/Demux Switch With Single Enable and ESD Protection 10-VSSOP -40 to 85Electrical Characteristics. 612.2 Community Resources...... 176.7 Switching Characteristics...... 6 ..


TPIC6259-TPIC6259DW-TPIC6259DWR-TPIC6259DWRG4-TPIC6259N
8-Bit Addressable Latch
1.5-A Pulsed Current Per Output Output Clamp Voltage at 45 V Four Distinct Function Modes Low Power Consumption
description

This power logic 8-bit addressable latch controls
open-drain DMOS transistor outputs and is
designed for general-purpose storage applica-
tions in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of storing single-line
data in eight addressable latches with 3-to-8
decoding or demultiplexing mode active-low
DMOS outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
address lines are changing. In the 3-to-8 decoding
or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are
high. In the clear mode, all outputs are high and unaffected by the address and data inputs.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10,
11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the
logic and load circuits.
The TPIC6259 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DRAIN0
DRAIN1
DRAIN2
DRAIN3
LGND
PGND
DRAIN7
DRAIN6
DRAIN5
DRAIN4
PGND
FUNCTION TABLE
LATCH SELECTION TABLE
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