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TPA0152 from TI, Texas Instruments 14pcs , TSSOP24,Stereo 2-W Audio Power Amp with Digital Volume Control
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TPA0152 TI N/a 14
SLOS246F–JUNE 1999–REVISED SEPTEMBER 2004Terminal FunctionsTERMINALI/O DESCRIPTIONNAME NO.BYPASS 11 Tap to voltage divider for internal mid-supply bias generatorIf a 47-nF capacitor is attached, the TPA0152 generates an internal clock. An external clock canCLK 17 Ioverride the internal clock input to this terminal.A momentary pulse on this terminal decreases the volume level by 2 dB. Holding the terminal low forDOWN 3 I a period of time will step the amplifier through the volume levels at a rate determined by the capacitoron the CLK terminal.1, 12,GND I Ground connection for circuitry. Connected to thermal pad13, 24LHPIN 6 I Left-channel headphone input, selected when SE/BTL is held highLIN 10 I Common left input for fully differential input. AC ground for single-ended inputsLLINEIN 5 I Left-channel line negative input, selected when SE/BTL is held lowLOUT+ 4 O Left-channel positive output in BTL mode and positive in SE modeLOUT- 9 O Left-channel negative output in BTL mode and high impedance in SE modeThe input for PC-Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave isPC-BEEP 14 Iinput to PC-BEEP or PCB ENABLE is high.PV 7, 18 I Power supply for output stageDDRHPIN 20 I Right channel headphone input, selected when SE/BTL is held highRIN 8 I Common right input for fully differential input. AC ground for single-ended inputsRLINEIN 23 I Right-channel line input, selected when SE/BTL is held lowROUT+ 21 O Right-channel positive output in BTL mode and positive in SE modeROUT- 16 O Right-channel negative output in BTL mode and high impedance in SE modeInput and output MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output isSE/BTL 15 Iselected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdownSHUTDOWN 22 Imode.A momentary pulse on this terminal increases the volume level by 2 dB. Holding the terminal low forUP 2 I a period of time will step the amplifier through the volume levels at a rate determined by the capacitoron the CLK terminal.Analog V input supply. This terminal needs to be isolated from PV to achieve highestDD DDV 19 IDDperformance.Thermal Pad Connect to ground. Must be soldered down in all applications to properly secure device on PC board.(1)ABSOLUTE
TPA0152APWR TI

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