TP3120J ,7 V, digital line interface controller (DLIC)Features
I A complete interface controller for up to 32 subscribers
of a digital switching syst ..
TP3122J ,7 V, digital line interface controller (DLIC)block diagram (Figure
" displays this tri-port arrangement. First, the DLIC controls
the space an ..
TP3155N ,Time Slot Assignment CircuitTP3155TimeSlotAssignmentCircuitSeptember1993TP3155TimeSlotAssignmentCircuitGeneralDescription
TP3155V ,Time Slot Assignment CircuitTP3155TimeSlotAssignmentCircuitSeptember1993TP3155TimeSlotAssignmentCircuitGeneralDescription
TP3204N ,+/-5 V, SLIC-MC magnetic compensation SLICGeneral Description
The TP3200 and TP3204 are monolithic Bipolar integrated
circuits intended f ..
TP337A , Thermopile Infrared Sensor
TQ2SA-L2-3V-Z , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2SA-L2-4.5V-Z , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2SA-L2-5V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2SA-L2-5V-Z , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2SA-L-3V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2SA-L-3V-Z , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TP3120J-TP3122J
7 V, digital line interface controller (DLIC)
National
SemiconductOI
Corporation
' .-/‘ caklfr-
PRELIMINARY
December 1985
Q50 7%,! - 7
TP3110/TP3112/TP3120/TP,3qat
Digital Line Interface Controllers (DLIC)
General Description
The TP3110, TP3120, TP3112, TP3122 Digital Line Inter-
face Controllers (DLIC) are general purpose switching com-
ponents primarily intended to serve as controllers of sub-
scriber line, service and trunk circuit cards of a digital
switching system. They are also useful as general purpose
data controllers for data switching and multiplexing applica-
tions.
The DLIC performs a three-way control function when used
for digital switching applications. The block diagram (Figure
" displays this tri-port arrangement. First, the DLIC controls
the space and time switching function between subscriber
line PCM CODECs/filters (COMBOTM) and the switching
system time division multiplex (TDM) highways. Second, the
DLIC controls the flow of information between the per line
circuit devices and the line card's local processor. Last, it
performs all protocol control functions, using the HDLC pro-
tocol format, for information passing between the local line
card processor and the main switching system processor
(or any other system processor).
The DLIC is configured with a parallel interface for the per
line and local processor circuits and with full duplex multiple
port serial highways for the system interface. All system re-
lated communications with the DLIC controlled circuit card
are handled via channel assignments on the serial TDM in-
tertace. In this way, all system data communications, sub-
scriber PCM, data, signaling and system control information
are transported and switched with a single network. This
approach improves the overall flexibility and modularity of
the total system design.
The DLIC contains a time-slot memory map for up to 128
duplex TDM channels, four high speed serial port transceiv-
ers, interface logic to allow the local processor to communi-
cate with the per line circuit devices (COMBO circuits and
the SLIC), a complete HDLC protocol controller for system
control messages, a vectored interrupt controller for the
HDLC protocol, signaling and timing control and finally, a
buffer memory for per line signaling data.
Features
gt A complete interface controller for up to 32 subscribers
of a digital switching system
I! Performs all time division multiplex (TDM) channel as-
signments for the circuit card it controls
2 Tx and Rx TDM ports (TP3110, TP3112)
4 Tx and Rx TDM ports (TP3120, TP3122)
Interfaces TP3051/6 parallel CODEC/Filter COMBO
Only 1 Time Slot delay
System control uses the HDLC protocol with all zero in-
sertion/deletion, checksum and flag control functions
performed by the DLIC
II Assignable addressing plus a "broadcast" address al-
lows up to 255 controllers per subsystem control group
without address field overlap
n Master mode allows DLIC to function as the group con-
troller
II Single 5V power supply operation
System Diagram
IP3057. "’3066
BDDEC/FILTER
CHIP SELECT
ADDRESS
DECDDER
SUBSCRIBER
Af ERFACE
MIC0PR0CESSim
MA0fWttliE ClDCK
ADDRESS ENAELE
TP31"! TNIN
TF3“? TPZIZZ
' ( " ' SERIAL
INTERFACE
CMTROL
PHOTDCUL
CDNTROL
SWITCHING
NETWORK
CONTROL
SYSIEM
CLOCKS
CONTROL
TL/H/6699-1
FIGURE 1. DLIC Signal Flows
TRI-STATE' Is a rsgtstaved trademark at National Semiconductor Corp.
COMBOW IS a trademark of National Semiconductor Corp,
@985 National SemiconductorCorporatxon TL/H/6699 l RRD-B20M125/Pnnted in U S A
(OI'ICI) SJalIO-llll<)() 9994191U| 9U!'I |91!5!C] ZZLSdl/OZLEdl/Zl l8dl/Ol LEdJ.
Absolute Maximum Ratings
Specifications for Military/Aerospace products are not
contained In this datasheet. Refer to the associated
Operating Temperature
- 25°C to + 70''C
Range (Ambient)
reliability electrical test specifications document.
VDD Relative to vss 7.0V
Voltage at Any Input or Output VSS - 0.3V to VDD + 0.3V
Storage Temperature Range (Ambient) -65'C to + 15ty'C
Maximum Lead Temp.
(Soldering, 10 seconds) 300°C
DC Electrical Characteristics
Unless othe . limits printed in BOLD characters are guaranteed for VDD = +5V t5%, vss = GNDD (digital
ground A = 0°C to +70°C correlation with 100% electrical testing at TA = +25°C. All other limits are assured by
correl Wit o er production tests and/or product design and characterization.
Parameter Conditions Min Typ Max Units
Input Voltage Levels
VlH, Logic High 2.0 V
I/c Logic low 0.7 V
Output Voltage Levels IOUT = 10 “A (Note 1) 4.0 V
VOH, Logic High [OUT = 100 “A 2.4 V
VOL, Logic low IOUT = -2.0 mA 0.4 V
TR1-STATE8 Leakages
HP Bus V = VDD - " 0A
V = GNDD soo pLA
Data Bus V = VDD - " FLA
V = GNDD soo pA
Input Currents
All Non-TRI-STATE Inputs 0 < VIN < VDD - " " ps/N
Pin Capacitances
Inputs 10 pF
Outputs 15 pF
TRI-STATE Busses 15 pF
Power Dissipation Temperature = 25''C
VDD = 5.0V 250 330 mW
Master Clock = 2 MHz
No Outputs Loaded
Note 1: Tested at 5.0V t OV,
AC Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VDD = +5V i5%, Vss = GNDD (digital
ground), TA = (Y'C to +70°C by correlation with 100% electrical testing at TA = +25°C. All other limits are assured by
correlation with other production tests and/or product design and characterization.
Parameter Conditions Min Typ Max Units
Clock Inputs
Master Clock Frequency 2.2 MHz
Master Clock High , BS ns
Master Clock Low t BS ns
Frame Clock Frequency 8 kHz
Frame Clock Duty Cycle (Note 2)
Clock Rise/Fall Times 20 ns
Data Bus Timing (Figure a
too, Clock Delay TO ns
tEL, Address Enable Low TO ns
15H. Address Enable High TO ns
IAV, Address Output Valid 1 so ns
tDV, Data Output Valid 330 ns
top, Data Bus Float 20 BO ns
tos, Data In Set-Up so ns
tDH, Data In Hold 20 ns
Note 2: Frame clocks FT, and f. are low during only one clock cycle of a transmit or receive frame, respectively, Each must go low shortly before the rising edge of
the first clock cycle ot a frame and return high shortly after the same clock edge, i.e., both edges of the frame clocks must be nominally aligned with falling edges of
Master Clock,
AC Electrical Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VDD = +5V t5%, vss = GNDD (digital
ground), TA = 0°C to +70°C by correlation with 100% electrical testing at TA = +25''C. All other limits are assured by
correlation with other production tests and/or product design and characterization.
Symbols Parameter Conditions Min Max Units
tFL Serial Port Timing (Figure 2) , so ns
Frame Clock Low
tFH Frame Clock High 1 so ns
tpv Port Output Valid 80 200 ns
tpVH Port Output Hold 35 ns
tps Port Input Set-Up 65 ns
tpH Port Input Hold ao ns
tSL Output Strobe Low 1 so ns
tSH Output Strobe High 1 so ns
Icy Microprocessor Interface Timing (Figure 3) 1.0 Jrs
Cycle Time
u ALE Pulse Width 1 " ns
tAS ALE to m Output 1 30 ns
tcc o-s Pulse Width 300 ns
tAL Address Set-Up to ALE TO ns
tLA Address Hold from ALE so ns
tDw Data Set-Up to D3 250 ns
two Data Hold from D-g 1 s ns
1RD Data Out Delay 270 ns
tDH Data Out Hold BS ns
trot, Data Ready Low soo ns
tDD Data Ready Delay Any register Read/ TOO ns
TP3110, TP3120 Write operation
only except Interface
Register in one-
shot mode
tDD Data Ready Delay Signaling Memory TOO + ns
TP3110, TP3120 Read/Write 6 It Tmutor dock
only operation
tDD Data Ready Delay Interface Register Depends on the con- Depends on the con-
TP3110, TP3120 one-shot Read/ tent of the Time-Slot tent of the Time-Slot
only Write operation Map (See Table ll) Map (See Table II)
Nate 3: AC characteristics measured at VOH = 2 0V and VOL = 0.7V. Load conditions are:
(a) Data Bus, Ft EM/CNTL, R/W Output, and Address Outputs
(b) Serial Output Ports, Output Strobes and AE Output
CLOAD = 200 pF
CLOAD = 50 PF
RLOAD = 2 kit to VDD
CLOAD = 150 pF
CLOAD = 80 PF
(c) Microprocessor Bus TRI-STATE Imes
(d) Interrupt Request and Data Ready Outputs
Connection Diagrams
Dual-in-Line Package
Dual-in-Line Package
Ilgs _ ?S- V00 Ifss --) V ' Am
P10 _ 'ii'" Ph N -7 F Ph
Mt - - DE! M? --- - PI;
T_-r'; ' M8 mu --i'; -v- P12
080 -s' "iii- IIS, 080 - i Na
Cut _ i 050 cu _5 i P02
" H, a. pth " ..2 .3; P01
’77 ' Hh “—9 -e- P00
- c, Ti' '7 033 n -To' "i7 Mt
R/ W -Ti' mua/ F mu rt/w T "3120/ b"-'.- 034
M80 - mm - 035 M30 - mm 2.L mas
MM 2l. l 036 Milt i A 086
wrt-'?. 2.. B87 M82 -l.?. l 037
M83 3 L A04 M83 i 1 AIM
MM -lr',' F,'? MBA+Z -,i,li- Ana
MM-c, J-J-Mi! MM-la -lioi?
try-F, Fer: mas+; 1 Alll
IT-rt FAD!) "T-t ",2,-i,'-iun
" "Gi' '7 NOTE I 05 TI] - NOTEI
ALE - m ALE - 'iL1., m
TL/H/6699-2 TL/H/6699-3
Top View Top View
Note t: Pin 22 = DR on TP3110, TP3120 N
Pin 22 = PCM/CNTL on TP3112, TP3122
Pin Descriptions e - -
SYSTEM INTERFACE PINS
Symbol Description
CLK Master Clock Input. This clock
determines the serial port data
rates and is also used to control
the data flow over the line circuit
Data Bus.
Poo-pos Serial Port Outputs. These out-
puts are the main TDM transmis-
sion ports tor the DLIC. The sig-
nal transmitted over these out-
puts must be inverted once be-
fore it is applied to a DLIC Serial
Port Input (PIO-Pla). P02 and
P03 are available only on the
TP3120 in lieu of (tik and O-s,.
Serial Port Inputs. These inputs
are the main TDM receive ports
for the DLIC. Pig and P13 are
available only on the TP3120
and TP3122 in lieu of DES and
P10 - Pl:,
Symbol
Co% - tbt,
Description
Output Strobes. These active-
low outputs indicate when P00
and POI respectively are trans-
mitting valid data. These outputs
are not present on the TP3120,
TP3122.
Master Transmit Frame Sync.
All Serial Port Output transmis-
sions are synchronized by this
signal.
Master Receive Frame Sync. All
Serial Port Input receptions are
synchronized by this signal.
5 VDC power input pin.
Digital Ground Power Input Pin
(GNDD). Ail DLIC signal levels
are referenced to the voltage
level at this pin.
Pin Descriptions (Continued)
SUBSCRIBER CIRCUIT INTERFACE PINS
Symbol Description
DBO-DB7 Bidirectional eight-bit subscriber
circuit interface bus. This bus
normally handles the per line
PCM COMBO data flowing to or
from a TP3051/TP3056 parallel
I/O COMBO circuit.
Data Type DB0 DB?
PCM Sign Bit LSB
Control Data CO C7
DB8-DB9
ADO-AD4
Additional Data Bus I/O pins for
the 80 kHz channel option ot the
DLIC. These two functions are
not available on the TP3120
(see P02, P03, Pl2 and Pls).
DB9 becomes the last bit of
each time slot on each serial
Subscriber circuit address out-
put pins. These pins are used to
select one of 32 different sub-
scriber or special service circuits
associated with the DLIC. A04 is
the MSB.
An active low output that indi-
cates a stable and valid sub-
scriber circuit address on pins
ADO through AD4.
Data Bus read/write select out-
put and COMBO master clock.
The A/w output frequency is
one-halt of the main clock input
frequency. A read operation on
the DLIC Data Bus (reading an
external device) occurs while
this clock is low and the corre-
sponding write operation occurs
while it is high.
MICROPROCESSOR INTERFACE PINS
Symbol
MBO-MB7
PCM/CNTL
Description
A bidirectional interface bus
used by a local processor to
control all DLIC operations. Ad-
dress, control and information
data flow between DLIC and its
associated microprocessor will
pass over this bus. MB? is the
Address Latch Enable input pin.
it is used by the DLIC to deter-
mine when address data is
crossing the MBO-MB7 Micro-
processor Bus.
Data Strobe input pin. A low true
input signal pin to indicate when
data is crossing the MBO-MB7
Microprocessor Bus.
Interrupt control output pin. A
low true output that indicates
when a DLIC generated interrupt
is active.
Data Ready output pin. This sig-
nal goes low on the falling edge
of E when data is written to or
read from the DLIC. It goes back
high again (a) when the write op-
eration has been executed in..
side the DLIC or (b) when the
previously addressed data is
available at the output of the
The primary use of this signal is
for Signaling Memory or Inter-
face Register Read operations,
since for these operations the
addressed data may not be im-
mediately available.
FCN/controt output pin. This
signal is normally low and goes
high during an interface instruc-
tion in NOP mode. Thus the
PiM/CNTL inputs of up to 32
TP3051 or TP3056 COMBO de-
vices can be driven by this out-
put, leaving all address outputs
ADO-AD4 available let decoding
32 a lines.
F—’ BEGIN mmsmn (on RECEIVE) FRAME
MASTER 1 \ f \ }
CLOCK [cm / F../
_. lFH
FRAM_E
svnc (F. on F.)
non/wnns / \ / _'
CLOCK (fi/W)
Anong§§
ENABLE (AE)
7 -' l-ti mm .5
2621/ . .y H-C ADDRESS VA‘LID ,/
Aonasss :
ADO-ADd) ::2~
AND M/CNTL
SYNCHRONOUS I
DA” BUS
(DBU-DB'I)
READ CYCLE WRITE CYCLE
a KL .__ (TYPICAL) ‘ (TVP‘CAL) —~ 13“
smAL Pom
ourrur smog:
SERIAL ourrm
mm (1 or a)
080 X DB1 f 082 :X K DES L D56 x DB7 W
' SERIAL INPUT
mm (1 or 4)
TL/H/SSQQ—d
fl DBI W 082
‘The Input and output data bii coinc-dence :5 true only I! E and FF. ave phase synchronous.
(PI) ""
FIGURE 2. Synchronous Data Bus and a Serial Port Transceiver Signal Flow
Timing Waveforms
ADDRESS LATCH
ENABLE (ALE)
DAM SIROBE
MICROPHOCESSDR 4'
BUS 5".
DATA READY
(NOTE 1)
(NOTE 2)
MICRO WRITING IO DLIC MICRO READING ULIC DATA
[ODD ADDRESS) (EVEN ADDRESS)
TL/H/6699-5
FIGURE 3. Microprocessor Interface
Note 12TP8110, TP3120 only.
Note 2: For any Read or Write operation Whlch Is not related to me Intenace Register or to the Signaling Memory. the stale of line DR can be qgnoved by me Microprocessor,
Timing Waveforms (Continued)
Functional Description
Referring to Figure 4, the primary purpose of the DLIC is to
control the flow of data between three I/O interfaces. These
interfaces are the System Interface, COMBO (or other sub-
scriber circuit) Interface and the Microprocessor Interface.
Data that moves between the COMBO Interface and the
System Interface. In this case, the serial output ports must
be used with open-collector or open drain line drivers be-
cause the output Strobes are not available for TRI-STATE
output control. Otherwise, all aspects of these parts are
identical.
System Interface is converted tr’om an eight or ttrrbit paral- " -Surnmarizing, I
lei tormet te, a synchronous senat format. In addition, up to a TP31t0, TPM20,
four bidirectional serial transmission interfaces are included Feature.
. . . _ TP3112 TP3122
m this first data movement group. Data that moves between N " 49m C OM O
the Microprocessor Interface and the System Interface is ' _ I B yes no
processed by Transmit and Receive High-level Data Link Interface bus
Control (HDLC) protocol controllers. This data is always in q Output strobes for yes no
an eight-bit format with two "dont care" stuffing bits if nec- P00 and PO,
essary for ten-bit compatibility. The third and final type of I l/O ports Plg. Pls no yes
data movement is between the COMBO Interface and the and Pth, P03
Microprocessor Interface ports. This movement allows inter-
action between the synchronous data flow of the COMBO to
System Interface bus and the asynchronous flow of the Mi-
croprocessor Interface bus. A description of these data
movements and their relation to the circuit blocks of Figure
4 is the main purpose of this Functional Description.
The DLIC is available in four configurations. The TP3110
and TP3112 are arranged with a ten-bit wide COMBO inter-
face and only two System Interface port circuits. These two
port circuits include separate serial input and output high-
ways and individual output strobes (W0 and tBi) to indi-
cate when the P00 and POI signals are valid. The TP3120
and TP3122 DLIC eliminate two bits of the ten-bit COMBO
Interface and the output strobes to provide a four-port
COMBO INTERFILCE 10 BITS (OR a BITS
The DLIC is composed of seven major circuit blocks as list-
ed below. The interaction between these circuit functions
and the three interface ports will be described separately.
The DLIC circuit blocks are:
1. Time Slot Map
t Serial Port Transceivers
. HDLC Protocol Logic
. Interface Register and Controller
. Vectored Interrupt Control Logic
. Signaling Memory
. Main Controller
\IO‘JUTAQM
} gm" mtgmca
l ,/,/,/’l, ’1 // //rt " iiif" " 2?
IO BO-M-- a 10 / 10
a 8 ans xm f" ti - -1
DATA BUSZ i10S / . lKTERFhCE pr ( MESSAGE
Mot an 87 REG am PROTOCOL I xm MII I
- f aumn nurrsn
t / MN common.
M - A Cr" Cd "ii" I pom -L, OSUPsnnt mun
A3 - l , I W” I ' N
M _ ADDR . menace 7 . A
m - MUX CONTROL '2i", l SIG BUFFER PORT m
. " , -
Ail - " " " REC "
W/CNIL - I
At " n SIG BUFFER
.0. " "
ADDR T SIGNALING Q Inn J I
RE - TIME SLOT / = AND I MEMORY A m
R/w - CONT80LLE8 "'. CONTROL M x2 ,
SEE mm: 3 c; k - - - -
", " I F 84 PORT CIRCUITS
TIME I TS ". on (h i) tlo l
,c' " t A
SLOT AOOR '7V /, /rt - f,” // " " " " ' . / ' 5V , IIN;
mm POINTER 4.1 ' " " L¢ ' if f r f GFl0tH--1lss
255x7 I am l Fd I Q " I 124
wt— cultlt
C .- mm
. I ( f . ,/ INTERRUPI
'r's' /y _ _ '", ' Anna T Fl Anna MAIN
f mn Aliflls OEC00E coumuusn q F,
y CONTROL I H I r.
ha 1 t t (
MICROPROCESSOR pr nus rm ALE 65 on
TL/H/6699-6
FIGURE 4. DLIC Block Diagram
Functional Description (Continued)
TIME SLOT MAP
The Time Slot Map and its associated circuitry control all of
the synchronous data movements in the DLIC. The Map is
organized as 256 seven-bit registers, each register directly
corresponding to one clock cycle of the master input clock
when in the eight-bit per channel format. For channels pro-
grammed to operate at ten bits per channel (as will be de-
scribed later), the first eight clock cycles of each channel
correspond to eight Map instructions and the last two cycles
are skipped by the Time Slot Map. Each Map register can
hold an instruction which will cause one of four basic opera-
tions. See Table VII tor a listing of the Time Slot Map in-
struction set.
The data entered into the Map is arranged as a two-bit in-
struction code and a tive-bit external device address code
(i.e., COMBO, or SLIC select address). An eighth bit, not
actually stored in the Map, is derived from an internal read/
write clock that alternates data bus operations from read to
write. This internal clock is exactly one-half the main clock
frequency and it forces adjacent instructions from the Map
to be read and write instructions.
Map addressing determines the actual time or space divi-
sion switching function to be performed by the DLIC. As
shown in Figure 5, the Map addresses are arranged so the
LSB determines serial transmission direction. The next two
bits are decoded as the system interface port transceiver
address and the top five address bits select one of 32 time
slots in the frame. By loading a Time Slot Map register, the
position of the instruction within the Map will determine the
channel, port and direction of the data flow over the System
Interface, while the contents of the Map register will deter-
mine the source or destination of the data.
Time Slot Map instructions are executed sequentially and in
complete synchronism with the master clock. The Map con-
trol logic, however, does allow the instruction sequence for
transmit and receive operations to be skewed in time. Clock
inputs Fl, and E provide the DLIC Map with the timing rela-
tionship between the transmit and receive frames, respec-
tively. This arrangement requires bit synchronization be-
tween the System Interface serial transmit and receive
ports, but does not require frame or channel (time slot) syn-
chronization.
To accommodate frames of less than 256 clock cycles, a
maximum clock count register is loaded with a binary num-
ber for the maximum number of clock cycles per frame. This
number is always a multiple of eight minus one 0.6., 7, 15,
31...255).
An associated microprocessor accesses the Time Slot Map
through the DLIC Microprocessor Interface port. The access _
is a two step process to allow the synchronization of data
that must be written to or read from the Map. First, the mi-
croprocessor must write a Map address into the Address
Pointer Register (address 01 hex), see Table I. Next, the
microprocessor can execute a Map read (address 40 hex)
or write (address 41 hex) command to move data to or from
the Map. A read command must be executed a minimum of
125 }.LS after an address load to allow the desired Map data
to be "down-loaded" into the access holding register. A
write command can be executed immediately after an ad-
dress load, but further Map read or write operations must be
suspended for at least 125 }.LS or one frame period. This
pause allows the written data to be loaded into the proper
Map location during the next complete Map scan. To facili-
tate a Map reset operation, the Address Pointer Register will
automatically increment to the next address count at the
end of each Map write command cycle (again, address 41
hex). This feature allows the microprocessor to write 256
NOP instructions into the Map, one instruction load per
frame period, using only a single microprocessor write oper-
ation per cycle.
SERIAL PORT TRANSCEIVERS
Two or four serial port transceivers are provided for the
DLIC System Interface. Under control of the Time Slot Map,
data is either parallel loaded for serial transmission or paral-
lel read after serial reception. The exact timing for all opera-
tions is dependent upon the instructions in the Map and the
beginning of each TDM channel relative to the start of the
MAP ADDR . TIME SLOT
0 PORT o TRANSMIT INST o
1 PORT o RECEIVE INST
2 PORT I mmsmt INST
3 PORT 1 RECEIVE INST
- - - - - -
4 PORT 2 TRANSMIT INST
- - - - - -i
5 Pom 2 RECEIVE INST
- - - - - -
6 PORT 3 TRANSMIT msv
7 mm 3 RECEIVE INST
l? ETC I
248 PORT o TRANSMIT INST 31
249 PORT n RECEIVE INST
- - - - - _
250 mm 1 TRANSMIT msr
i- - - - - -
251 PORT 1 RECEIVE INST
- - - - - -
25? PORT 2 TRANSMIT INST
- - - - - --
253 PORT 2 RECEIVE lNST
254 mm a TRANSMIT INST
- - - - - _.
255 PORT 3 RECEIVE INST
TL/H/6699-7
FIGURE 5. Time Slot Map Organization
Functional Description (Continued)
frame. While all serial exchanges begin and end in align-
ment with the TDM channels, parallel exchanges are only
synchronized to master clock cycles. Incidentally, for normal
DLIC operation a channel is eight clock cycles long and the
first channel begins with the positive master clock edge
while the appropriate frame clock is low.
The idle state for any Serial Output Port is logic low. This
signal must be externally inverted to logic high before it can
be applied to a Serial Input Port on any DLIC. The inverted
signal corresponds to the idle channel code of a PCM
COMBO and the idle or abort sequence of the HDLC proto-
col. The normal hardware arrangement would use an invert..
ing bus driver between the DLIC Serial Output Ports and the
system backplane highways, and no inverter between the
backplane and the DLIC Serial Input Ports.
In the ten-bit operating mode, the beginning of channel one
is still the rising clock edge while the appropriate frame
clock is low. The length of each channel, however, is ten
bits or clock cycles and for a full 32-channel frame, 320
clock cycles are required. The transceivers will serially shift
the extra two bits per channel after the normal tsight-bit se-
quence is complete.
Transmission order for the serial System Interface is always
LSB first, for data and sign bit first for PCM. This is compati-
ble with the normal protocol of PCM transmission. The or-
dering of the data from the parallel interface of the TP3051
or TP3056 PCM COMBOs is thus reversed from the normal
arrangement, and is shown below:
Serial Transmission Order Data Bus Order
First bit in or out DBO
Second bit DB1
Third bit DB2
Fourth bit DB3
Fifth bit DB4
Sixth bit DB5
Seventh bit DB6
Eighth bit DB7
Ninth bit (10-bit mode only) DB8
Tenth bit (IO-bit mode only) DB9
Whenever the ninth and tenth serial bits are delivered to or
from the signaling memory circuit block (a programmable
option), the ninth bit internally passes through the DLIC as
bit DO while the tenth bit passes as D1 (Figure 4). Over the
Microprocessor Interface bus, these bits correspond to MB0
and MBI respectively.
PROTOCOL LOGIC
System control messages are transmitted between the main
processor and the DLIC local processor by way of System
Interface TDM channels. This data passes through the DLIC
under direct control of the Time Slot Map. Because the in-
tegrity of this control information is very important to the
total system operation, the DLIC includes High-level Data
Link Control (HDLC) protocol circuits to process these con-
trol messages. These are independent Transmit and Re-
ceive HDLC circuits that allow simultaneous both-way con-
trol messages if required.
The HDLC format used in the DLIC follows the CCITT X.25,
Section 2.1 and 2.2 recommendation. This recommendation
calls for an opening flag sequence of 01111 1 10 followed by
the device address, control, data, checksum and closing
flag fields. The closing flag of one message can be used as
the opening flag to the next message. To avoid the uninten-
tional simulation of a flag sequence, the DLIC will insert a
zero after any string of five ones except where a flag or
abort code is desired. Again, this is in conformance with the
CCITT recommendation.
Before starting a transmit message the microprocessor
must first load the DLIC Address Register with the unique
address for that subscriber line card; write the Time Slot(s)
for the message channel in the Time Slot Map; and enable
the necessary interrupts (see Table V). Then the first data
byte must be loaded in the Transmit Message Register. The
message channel is activated by setting Control Register bit
5 high (see Table III). An opening flag is transmitted in the
selected channel, then the DLIC address and then the first
data byte, with zeroes inserted according to the HDLC pro-
tocol. Each time the Transmit Message Register is emptied,
the DLIC automatically generates a "register empty" inter-
rupt to force the microprocessor into loading the next data
byte of the message. If the microprocessor responds to this
interrupt by turning the HDLC transmit logic off, the DLIC will
close out the current message with the CRC checksum and
a closing flag. Failure to service this interrupt before the
next message Time Slot arrives will result in the abort se-
quence of all rs being transmitted.
For receive messages the microprocessor must first load
the associated DLIC registers as described for the transmit
section. The DLIC monitors the message channel until an
opening flag is detected, then compares the address field
with the contents of the DLIC Address Register. If there is a
match, or if the address field contains the broadcast ad-
dress, Hex FF, the message is accepted. (Inserted zeroes
are automatically deleted.) As each message data byte is
received it is stored in the Receive Message register and an
interrupt generated to summon the microprocessor. When
the register is read, the interrupt signal is reset to await the
next data byte. If the interrupt is not serviced before the next
data byte arrives, or if an abort sequence is received, the
receive CRC checksum will be corrupted to indicate that the
message is not valid. The receive protocol logic automati-
cally computes the CRC checksum on the incoming mes-
sage and compares it with the CRC field (which is not
known until the closing flag is detected) to determine the
final interrupt for this message, i.e.. Checksum Correct or
Checksum Incorrect
It should be noted that the DLIC can receive only a single
control message at a time (i.e., the receive message chan-
nel must be one channel of one serial highway). it can, how-
ever, transmit a control message over one, two, three or
four ports simultaneously, although the same channel must
be used for each of the ports. This is a useful feature that
simplifies overall system design.
MASTER MODE
This mode allows the DLIC to be used as the master con-
troller for a group of line cards connected to a common
backplane. lt forces the receive protocol logic to ignore the
contents of the address field on an incoming message so
that it will accept a message from any source. Internally the
address comparison is inhibited and the address byte is
Functional Description (Continued)
forwarded to the microprocessor in the same manner as a
data byte.
The transmit HDLC logic operation is not changed in this
mode. Before transmitting a new message the microproces-
sor must load the DLIC Address Register with the ttestina-
tion address. Alternatively, a message can be "broadcast.
ed" to all DLIC's in a control group by setting the address
field to hex FF. Master Mode is selected by setting Control
Register bit 4 high.
INTERFACE REGISTER AND CONTROLLER
This circuit block provides a direct data access path be-
tween the DLIC associated microprocessor and any of the
circuit devices connected to the COMBO Interface bus. This
allows the two internal data busses, which are operating in
asynchronism with each other, to communicate control and
signaling information through the DLC. This need for addi-
tional access ports on the per channel circuits is eliminated
with this communications scheme.
The Interface Register operates in one of two control
modes and handles the flow of data in only one direction at
a time. Data written into the register from the Microproces-
sor Interface bus can be moved onto the COMBO Interface
bus during either the next available Time Slot Map NOP
(direct mode) or when a particular Map instruction is execut-
ed (frame mode). in a similar fashion, data can be moved in
from the COMBO Interface bus to be written onto the Micro-
processor Interface bus in either the direct or frame mode
fashion. Control of the Interface Register is handled by
matching instructions in the Time Slot Map and Interface
Register Controller. See Table II for additional details.
Control data is written to DLIC address 03 hex. The micro-
processor can read the Interface Register with hex address
42 and it can write to the Register with hex address 43.
Reading the Register from either the Microprocessor or
COMBO Interface busses does not alter its contents. Any
operation which takes place during a Time Slot Map NOP
will occur only once. The Register Controller will reset to a
NOP control condition after the "one-shot" execution. The
data READY output (TP3120 and TP3110) indicates the
pending nature of this control cycle by remaining low from
the time the instruction is loaded until execution is com-
plete. On the TP3122 and TP3112 only, the PC-M/CN"
output goes high when a "one-shot'' control instruction is
being executed. Operations which occur as the result of a
match between a Time Slot Map instruction and the control
byte loaded into the Interface Register Controller will occur
every frame and must be halted by direct command from
the microprocessor. This latter operating mode is interrupt
driven and is useful in generating PCM test signals with the
local microprocessor.
INTERRUPT LOGIC
The DLIC contains an on-board Vectored Interrupt Control-
ler. This Controller will process the seven built-in interrupts
ot the DLIC. In addition, these interrupts are prioritized so
that important operations are never missed. See Table V for
more information.
The DLIC microprocessor can directly read or write the sev-
en DLIC interrupt registers. This allows a specific program
address to be loaded into the DLIC interrupt control logic so
that the occurrence of the interrupt can cause a program
vector to be read from the DLIC by the microprocessor. The
DLIC read address for a pending interrupt is 00 hex. The
information read with the 00 address is then directly used by
the microprocessor to compute an address jump to the ap-
propriate software routine to service this interrupt. The ad-
dress 00 read operation will automatically reset and clear
the interrupt request and its output signal on the INTR line.
Interrupts that require simultaneous service are handled in
the priority order given in Table V. Additional features of this
logic section include a single DLIC Command Register con-
trol bit to activate and deactivate the interrupt logic output
signal and a control register within the interrupt logic block
for selective masking of individual interrupts. it should be
noted that turning all interrupts off with the single control bit
does not disable the generation of the interrupts inside the
DLIC. When the control bit reactivates the interrupt output
line, any interrupts that have occurred during the idle state
will immediately request service in the proper priority order.
However, masking an interrupt off by storing a zero in the
proper place within the interrupt control register (address 3F
hex) will totally disable the interrupt. Internal circuitry will not
recognize the activity that normally causes the interrupt re-
quest and the interrupt, when enabled, starts from a reset
condition.
SIGNALING MEMORY
This memory block operates as either a butter store for the
two bits of the ten-bit 80 kHz channel or as a general pur-
pose RAM. DLIC control bit D3 of Table III will determine the
operating state. In either state, the Signaling Memory is ar-
ranged as 64 two-bit cells that interface the microprocessor
bus through the two least significant bits MBO and MBI.
Internal to the DLIC, these two bits are called DO and D1.
When the Signaling Memory is used for general storage, the
DLIC control bit D3 is set to zero. Each two-bit cell of the
memory is accessed with one of 64 read or write addresses
as shown in Table VIII. The interface between the Signaling
Memory function and the System Interface transceivers is
totally disabled while in this operating state.
While using the Signaling Memory RAM for general storage,
the extra two bits of the ten-bit serial channel System lnter-
face format can only be accessed through the DB8 and DB9
lines of the COMBO Interface bus. This means that only the
TP3110 and TP3112 can simultaneously operate with teni
bit serial channels and the Signaling Memory in the general
storage operating state.
When DLIC control bit D3 is high, the Signaling Memory
RAM is switched to an operational state known as Extended
Channel Signaling (ECS). In this operating mode, the data
for bits 9 and 10 ot a ten-bit serial channel are buttered by
the Signaling Memory. This data is not accessible through
the COMBO Interface bus pins DB8 and DB9 when ECS is
enabled. The extra two bits of data are accessible only
through the 32 transmit and 32 receive cells in the Signaling
Memory RAM. Each of the cells corresponds to an address
of the COMBO Interface bus. This allows any device con-
nected to this bus to utilize the Signaling Memory RAM,
loaded and unloaded through the DLIC microprocessor, tor
end-to-end system data communications at speeds of up to
16 kHz.
Functional Description (Continued)
MAIN CONTROLLER
While most of the DLIC features and functions are con-
trolled by the various circuit blocks already described, some
master control functions still remain to be explained. These
include the setting of overall frame timing and length, power
on reset conditions, and the initialization of Time Slot Map,
Signaling Memory and HDLC protocol control power-up
states. Also available through the DLIC main control are
status flags for the HDLC protocol logic and the interface
register.
Because of the pipelined architecture of the DUC, the Time
Slot Map is actually operated in a "look ahead" fashion.
This structure requires a maximum TDM frame length regis-
ter on the DLIC. It is microprocessor loaded during initial-
ization and it provides the DLIC with address counter
"wrap" information during less than full length TDM frames.
The DLlC maximum count is determined on a eight-bit per
channel basis. It the DLIC is set for ten-bit operation, the
maximum count is still related to eight bits per channel. This
is because the Time Slot Map will skip two clock cycles out
of every ten during this latter operating mode. The maximum
count register is set to the number of channels in a frame
(on one of the highways) times eight. As an example, a 24-
channel system would require a maximum count frame
length of 192 (24 x 8) and the DLIC maximum count register
would be set to hex BF which corresponds to the decimal
192 clock cycles per frame.
TABLE I. Microprocessor Interface
Hex . .
A d dress Description of Interface Data Flow
0 0 Microprocessor READ of current interrupt vector after detecting a logic low condition on
DLIC output W.
0 1 Microprocessor WRITE cycle to the address pointer register of the Time Slot Map
controller.
0 2 Not used.
0 3 Microprocessor WRITE cycle to the control logic of the Interface Register. See Table II.
0 4 Not used.
0 5 The WRITE cycle used by the microprocessor to load the DLIC Address Register.
0 6 Not used.
0 7 The WRITE cycle used by the microprocessor to set the maximum number of clock cycles
per frame.
0 8 Microprocessor READ of current DLIC status conditions.
0 9 Microprocessor WRITE cycle to set the DLIC Control Register. For addresses 08 and 09,
see Table III.
l Not used.
2 0 READ and WRITE operations to the Interrupt Vector Registers of the DLIC. See Table V.
4 0 A microprocessor READ cycle of Time Slot Map data. The Map address must be preset
using hex address 01 .
4 1 The complementary WRITE operation for hex address 40. See Table VII.
4 2 The microprocessor READ cycle of the Interface Register. Control conditions must be
preset with hex address 03.
4 3 The complementary WRITE operation for hex address 42. Control conditions are normally
set after this WRITE cycle.
Not used.
5 0 A microprocessor READ operation to retrieve data from the Receive Message Register
after the appropriate interrupt has been received.
5 1 A microprocessor WRITE operation to the Transmit Message Register. Again, the ap-
propriate interrupt will normally initiate this microprocessor operation.
Not used.
8 0 Microprocessor access to the DLIC Signaling Memory. Even addresses correspond to
READ cycles for the 64 two-bit memory cells while odd addresses correspond to comple-
F F mentary WRITE cycles. See Table Vlll.
Functional Description (Continued)
POWER-UP lNITIALIZATlON
During power-up initialization, the DLIC will automatically
clear its control register. This action will disable the Time
Slot Map and System Interface output ports, set the INTR
output high, deactivate the HDLC transmit protocol logic
and place the DLIC in the eight-bit per channel operating
mode. No other reset functions will occur. As described ear-
lier, the DLIC associated microprocessor is responsible tor
clearing the Time Slot Map, setting the interrupt vectors,
loading the DLIC Address Register, and in general, estab-
lishing all of the DLIC control and operating states. Through
the Control Register, the microprocessor can quickly acti.
vate and deactivate the major functions of the DLIC with a
single write operation to hex address 09.
TABLE II. Interface Register Control
D7 D 6 D5 :fta Ti, D 2 D 1 D 0 Description of Interface Register Control Operatlon
0 0 0 A control instruction to move data from an external device
into the DLIC Interface Register during the next Time Slot
Map NOP while the A/w line is low. This cycle will auto-
matically reset to a no operate state after execution.
0 0 t 1 The complementary operation to the above with the data
Address movement from the preloaded Interface Register into an
field for external device. Again, this is a one-shot operation.
0 1 devices 0 A control instruction to move data from an external device
connected into the DLIC Interface Register whenever this control
to the byte matches a Time Slot Map instruction byte. This in-
data bus struction remains in effect until manually cleared by the
l microprocessor.
o 1 1 The complementary operation to the above with the data
movement from the Interface Register into an external
device any time this control byte matches a Time Slot Map
instruction byte.
1 0 Don' t care 0 Reserved.
1 0 1 Reserved.
1 1 Don't care 0 No operation.
1 1 l 1 No operation.
TABLE III. DLIC Status and Control Data
Data DLIC Status Register DUC Control Register WRITE Cycle;
Bit READ Cycle; Address 08 Address 09
D0 Transmit Message Register empty. Enable Time Slot Map controller.
D1 Receive Message Register full. Enable FNrn (interrupt) request output.
D2 An Interface Register command is in effect. Enable the 10-bit/channel operating mode.
De HDLC opening receive flag detected. Enable Signaling Memory tor Extended
Channel Signaling.
D4 CRC error detected on incoming message. Enable Master Mode.
D5 HDLC receive logic in idle state. Enable HDLC Transmit Message Logic.
D6 HDLC transmit logic in the active state. Not used.
D7 HDLC transmit channel in the idle state. Should always be zero.
Functional Description (Continued)
TABLE IV. DLIC Control States
Function Control Register TP3110, 3112 TP3120, 3122 De cri tl
D? D3 D2 Option Option s 'p "m
Normal 0 0 0 yes yes Up to 32 eight-bit channels per frame on
each serial highway. No other options.
Ten-Bit 0 0 1 yes no 32 ten-bit channels/trame with bits 9 and
10 accessed through 10-bit data bus.
ECS 0 1 1 yes yes 32 ten-bit channeIs/frame with bits 9 and
10 accessed through the Signaling
Memory.
TABLE V. Interrupt Vector Registers
Hex Priorty Desert tion of Re Ister READ and WRITE 0 erations
Address Level p g p
2 0 5 Direct READ of vector register for Interface Register instruction executed interrupt.
2 1 WRITE operation for the same interrupt register.
2 2 4 Direct READ of vector register for Transmit Message Register empty interrupt.
2 3 WRITE operation for the same interrupt register,
2 4 1 Direct READ of vector register for Receive Message Register full interrupt.
2 5 WRITE operation for the same interrupt register.
2 6 2 Direct READ of vector register for Receive Message Checksum Correct interrupt.
2 7 WRITE operation for the same interrupt register.
2 8 3 Direct READ of vector register for Receive Message Checksum Incorrect interrupt.
2 9 WRITE operation for the same interrupt register.
2 A 6 Direct READ of vector register for End of Transmit Frame interrupt.
2 B WRITE operation for the same interrupt register.
2 C 7 Direct READ of vector register for End of Receive Frame interrupt.
2 D WRITE operation for the same interrupt register.
l X Not used.
3 E X READ operation for Interrupt Masking Register.
3 F WRITE operation for Interrupt Masking Register. (See Table VI for details).
Note: Interrupt priority levels are associated with the service order if simultaneous interrupts request attention via the microprocessor 00 hex address READ cycle.
All interrupts automatically reset only after the appropriate vector is read through this same 00 hex address.
TABLE VI. Interrupt Masking
tf Description ot Masking Control with Interrupt Mask Register
DO If high, Receive Message Register full interrupt is on.
D1 If high, Receive Message Checksum Correct interrupt is on.
D2 If high, Receive Message Checksum Incorrect interrupt is on.
D3 If high, Transmit Message Register empty interrupt is on,
D4 If high, Interface Register instruction executed interrupt is on.
D5 It high, End of Transmit Frame interrupt is on.
De If high, End of Receive Frame interrupt is on.
D7 Not used.
Functional Description (Continued)
TABLE VII. Time Slot Map Instructions
D7 D6 D5 Data BYE: D 2 D1 DO Description of Time Slot Map Instruction Code
0 0 0 Move data from an external device (e.g., parallel COMBO)
t to a serial port transmitter. The Map address identifies the
proper transmitter.
Address . _ .
O 0 t 1 Move data from a serial port receiver to an external device.
field for ' . _ .
devices The Map address identifies the proper receiver.
0 1 connecte d 0 Move data from an external device to the Interface
to the Register whenever a match occurs between this data byte
data bus and the contents of the Interface Register Controller.
0 1 l 1 Move data from the Interface Register to an external
device whenever a match occurs between this data byte
and the contents of the Interface Register Controller.
1 o 0 Move data from the Transmit Message Register, through
the protocol logic section to a serial port transmitter. The
t Map address identifies the proper transmitter,
1 0 Don't care (Note 1) 1 Move data from a serial port receiver, through the protocol
logic section to the Receive Message Register. The Map
address identifies the proper receiver.
1 1 0 No operation.
1 1 1 No operation.
Note 1: To minimize bus and system nose it IS recommended that thus held be set to all " 's.
TABLE VIII. Signaling Memory Addressing
Hex Description of Memory Access Description of Memory Access
Address with ECS Disabled with ECS Enabled
8 0 READ bits DO and D1 of cell READ signaling data received for external
number 0. device 0.
8 1 WRITE bits DO and D1 of cell Not used.
number 0.
B 2 READ bits DO and D1 of cell READ signaling data received for external
number I. device 1.
8 3 WRITE bits DO and D1 of cell Not used.
number l.
B E READ bits DO and D1 of cell READ signaling data received for external
number 31. device 31.
B F WRITE bits DO and D1 of cell Not used.
number 31.
C o READ bits DO and D1 of cell Not used.
number 32.
C 1 WRITE bits DO and D1 of cell WRITE into memory, external device 0
number 32. transmit signal data.
C 2 READ bits DO and D1 of cell Not used.
number 33.
C 3 WRITE bits DO and D1 of cell WRITE into memory, external device 1
number 33. transmit signal data.
F E READ bits Do and D1 of cell Not used.
number 63.
F F WRITE bits DO ad D1 of cell WRITE into memory, external device 31
number 63.
transmit signal data.
TP3051/56 080
DATA BUS
fiti/CNTL
fi/w n F
74HC154
PCM IN
16 COMBO‘S .
PCM OUT
TPSOSl/SG
?Ei/CNTL
1/4 x 701cm
ALE WR RD
INS 8048/49/50
‘ 0R FEi/CNTLIF TP3112 OR IP3122
SLIC CONTROL INTERFACE P2
TL/H/6699—6
FIGURE 6. Typical 16-Channel Line Card Application
Typical Application
tal Line Interface Controllers (DLIC)
TP3110/TP3112/TP3120/TP3122 D
Physical Dimensions inches (millimeters)
Lit. ' 113980
1.343‘2370
[--, - IM39-st.58t -
_g-,1ss-or-ii3-ar-sw3-4rarmrnme-ias,vr--oraariil
i) 062 I
"73969 (i)
PIN " I IDENT-\
0.550 mm
[11970 0.127)
tl-Ile-lt-OIL-JL-JI-s)!).''?.,!]]?])-')?-']?-')?-?]?-'])-').']
nus) 0.an
(0.152) (1.050
n. _ MAX (TH)
l "f1 l “3:321:33, l
l 1115-01“:
(15:14:14)
"09-il.il15 qc,
HI 025 (ngs-nzan f',,' 0.020
n.615 _ -____ t
Al 015 _ 0.015 mm P l Han 'tuno mm Ahilil3 (0.508)
l----- i --_-- -We "irtcCet-atls, - "l . mm
'lHi35 (1.505 L3811 (1540 4:154) (0.457 u‘um
(tsms Ar381 C.125-0,10
(1115-1555)
N“ ‘REV Er
Molded Dual-ln-Package (N)
Order Number TP3120J or TP3122J or TP3110J or TP3112J
NS Package N40A
LIFE SUPPORT POLICY
NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
to the user.
Nulonnl Schconductor Nutlonll SqtmktorttNtttttr NS lenn Ltd. N-Honll Somlconduclov National Sarttlettnttutttr" Nulonll Semiconductor
Corpontlon (3th 4-403 Ikebukuw. Hong Kong Ltd. Do Brull Lian. (Auulrallu) PTY, Ltd.
2900 Setmrconductor Dave Wttgttrrtdstrasw 193495 Tosmmavku. Southuu Aula lnrknung Av Bog Fana lea. 830 21/3 Hagn Street
P C) Box 58090 0-8000 Munchen 21 Tokyo WI. Japan Austin Yowev, 4th Hoot a Andar Bayswater, Vlclona 3153
Yel, (03) 988-2l31
FAX: 01riul?,98ir1700
Santa Clara. CA 9505243090
Tel HM) 72i-5000
rwx (91013393240
West Germany
Tel (089) s 70 95 Cl
Telex 522772
22-26A Austin Avenue
Ts-mshafsu Kowloon, H K
Tel 17231290 37243645
Cable. NSSEAMKTG
Yelex 52996 NSSEA HX
01452 Sao Paulo. SP Bvasal
Tel (55/11) 2125066
Tdex 39l-1131931NSBR BR
Australa
Ttrr (09) 729-6933
Telex M32096
Natrona) does not assume any responsmlllry for use of any Clvcunry described no arcutt palenl licenses are xmphed and Nahonal reserves the nght al any Ilme without notice lo change sad culcullry and specmcancns
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
TP3122J - product/tp3122j?HQS=TI-null-nu|I-dscatalog-df-pf-null-wwe
TP3120J - product/tp3120j?HQS=T|—null-nu|I-dscatalog-df-pf-nuII-wwe
TP3112J - product/tp3112j?HQS=TI-null-nu|I-dscatalog-df-pf-nuII-wwe
TP311OJ - product/tp3110j?HQS=TI-nuII-nu|I-dscatalog-df-pf-nulI-wwe
