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TP3076N-G from NS, National Semiconductor 874pcs , DIP , Alternate PN:TP3076NG,Combo II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications
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TP3076N-G NS N/a 874
Pin DescriptionV +5V ±5% power supply.CC±V −5V 5% power supply.BBGND Ground. All analog and digital signals are referenced to this pin.FS Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is appliedXto this input to define the start of the transmit time slot assigned to this device (non-delayed datatiming mode), or the start of the transmit frame (delayed data timing mode using the internal time-slotassignment counter).FS Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied toRthis input to define the start of the receive time slot assigned to this device (non-delayed data timingmode), or the start of the receive frame (delayed data timing mode using the internal time-slotassignment counter).BCLK Bit clock input used to shift PCM data into and out of the D and D pins. BCLK may vary from 64R XkHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK.MCLK Master clock input used by the switched capacitor filters and the encoder and decoder sequencinglogic. Must be 512 kHz, 1.536/1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK.VF I The Transmit analog high-impedance input. Voice frequency signals present on this input areXencoded as an A-law or µ-law PCM bit stream and shifted out on the selected D pin.XVF O The Receive analog power amplifier output, capable of driving load impedances as low as 300ΩR(depending on the peak overload level required). PCM data received on the assigned D pin isRdecoded and appears at this output as voice frequency signals.®D 1 This transmit data TRI-STATE output remains in the high impedance state except during theXassigned transmit time slot on the assigned port, during which the transmit PCM data byte is shiftedout on the rising edges of BCLK.TS 1 Normally this open drain output is floating in a high impedance state except when a time-slot is activeXon the D output, when the TS 1 output pulls low to enable a backplane line-driver.X XD 1 This receive data input is inactive except during the assigned receive time slot of the assigned portRwhen the receive PCM data is shifted in on the falling edges of BCLK.CCLK Control Clock input. This clock shifts serial control information into CI or out from CO when the CSinput is low, depending on the current instruction. CCLK may be asynchronous with the other systemclocks.CI Control Data Input pin. Serial control information is shifted into COMBO II on this pin when CS is low.Byte 1 of control information is always written into COMBO II, while the direction of byte 2 data isdetermined by bit 2 of byte 1, as defined in Table 1CO Control Data Output pin. Serial control or status information is shifted out of COMBO II on this pinwhen CS is low. 2TP3076TP3076
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