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| TP3071J from NS, National Semiconductor 1pcs,COMBO II Programmable PCM CODEC/Filter | ||||||||||
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| TP3071J from NS , National Semiconductor 500pcs,COMBO II Programmable PCM CODEC/Filter | ||||||||||
| applications on subscriber line and trunk cards. Using— Receive power amplifier drives 300Ωadvanced switched capacitor techniques, COMBO II com-— 4.096 MHz serial PCM data (max)bines transmit bandpass and receive lowpass channel filterswith a companding PCM encoder and decoder. The devices n Programmable Functions:are A-law and μ-law selectable and employ a conventional — Transmit gain: 25.4 dB range, 0.1 dB stepsserial PCM interface capable of being clocked up to — Receive gain: 25.4 dB range, 0.1 dB steps4.096 MHz. A number of programmable functions may be — Hybrid balance cancellation filtercontrolled via a serial control port. — Time-slot assignment; up to 64 slots/frame— 2 port assignment (TP3070)Channel gains are programmable over a 25.4 dB range in— 6 interface latches (TP3070)each direction, and a programmable filter is included to en-— A or μ-lawable Hybrid Balancing to be adjusted to suit a wide range of— Analog loopbackloop impedance conditions. Both transformer and active— Digital loopbackSLIC interface circuits with real or complex termination im-n Direct interface to solid-state SLICspedances can be balanced by this filter, with cancellation inexcess of 30 dB being readily achievable when measured n Simplifies transformer SLIC; single winding secondaryacross the passband against standard test termination net-n Standard serial control interfaceworks.n 80 mW operating power (typ)To enable COMBO II to interface to the SLIC control leads, an 1.5 mW standby power (typ)number of programmable latches are included; each may ben Designed for CCITT and LSSGR Pin DescriptionSee NS Package Number V28AV +5V ±5% power supply.CCV −5V ±5% power supply.BBGND Ground. All analog and digital signals arereferenced to this pin.FS Transmit Frame Sync input. Normally a pulseXor squarewave with an 8 kHz repetition rate isapplied to this input to define the start of thetransmit time slot assigned to this device(non-delayed data timing mode), or the start ofthe transmit frame (delayed data timing modeusing the internal time-slot assignmentcounter). 2 | ||||||||||
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| TP3071J/D NS TP3071J-D NSC TP3071J-D NS TP3071J-G NSC TP3071N-D TP3071N-D NSC TP3071N-G NSC,applicationsconfigured as either an input or an output. The TP3070 pro-n TTL and CMOS compatible digital interfacesvides 6 latches and the TP3071 5 l .. | ||||||||||
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