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TP3071AN-G from NS, National Semiconductor 15pcs , Alternate PN:TP3071ANG,COMBO II Programmable PCM CODEC/Filter
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TP3071AN-G NS N/a 15
TP3071AN-G 699pcs , DIP20 , Alternate PN:TP3071ANG,COMBO II Programmable PCM CODEC/Filter
Pin Descriptionprovided on the TP3071. Serial controlFS Receive Frame Sync input. Normally a pulseR information is shifted to or read from COMBOor squarewave with an 8 kHz repetition rate isII on this pin when CS is low. The direction ofapplied to this input to define the start of thethe data is determined by the currentreceive time slot assigned to this deviceinstruction as defined in Table 1.(non-delayed data timing mode), or the start ofCI This is a separate Control Input, available onlythe receive frame (delayed data timing modeon the TP3070. It can be connected to CO ifusing the internal time-slot assignmentrequired.counter).CO This is a separate Control Output, availableBCLK Bit clock input used to shift PCM data into andonly on the TP3070. It can be connected to CIout of the D and D pins. BCLK may varyR Xif required.from 64 kHz to 4.096 MHz in 8 kHzCS Chip Select input. When this pin is low, controlincrements, and must be synchronous withinformation can be written to or read fromMCLK.COMBO II via the CI/O pin (or CI and CO).MCLK Master clock input used by the switchedIL5–IL0 IL5 through IL0 are available on the TP3070.capacitor filters and the encoder and decoderIL4 through IL0 are available on the TP3071.sequencing logic. Must be 512 kHz, 1.536Each Interface Latch I/O pin may beMHz, 1.544 MHz, 2.048 MHz or 4.096 MHzindividually programmed as an input or anand synchronous with BCLK.output determined by the state of theVF I The Transmit analog high-impedance input.Xcorresponding bit in the Latch DirectionVoice frequency signals present on this inputRegister (LDR). For pins configured as inputs,are encoded as an A-law or μ-law PCM bitthe logic state sensed on each input is latchedstream and shifted out on the selected D pin.Xinto the Interface Latch Register (ILR)VF O The Receive analog power amplifier output,Rwhenever control data is written to COMBO II,capable of driving load impedances as low aswhile CS is low, and the information is shifted300Ω (depending on the peak overload levelout on the CO (or CI/O) pin. When configuredrequired). PCM data received on the assignedas outputs, control data written into the ILRD pin is decoded and appears at this outputRappears at the corresponding IL pins.as voice frequency signals.MR This logic input must be pulled low for normalD 0 D 1 is available on the TP3070 only; D 0isX X X operation of COMBO II. When pulledD 1 available on all devices. These Transmit DataX momentarily high (at least 1 μsec.), all®TRI-STATE outputs remain in the highprogrammable registers in the device are resetimpedance state except during the assignedto the states specified under “Power-Ontransmit time slot on the assigned port, duringInitialization”.which the transmit PCM data byte is shiftedNC No Connection. Do not connect to this pin. Doout on the rising edges of BCLK.not route traces through this pin.TS 0 TS 1 is available on the TP3070 only; TS 0isX X XTS 1 available on all devices. Normally theseX applicationsconfigured as either an input or an output. The TP3070 pro-n TTL and CMOS compatible digital interfacesvides 6 latches and the TP3071 5 latches.n Extended temperature versions available for −40˚C to+85˚C (TP3070V-X)Note: See also AN-614, COMBO II application guide.® ®COMBO and TRI-STATE are registered trademarks of National Semiconductor Corporation. 1999 National Semiconductor Corporation DS008635

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