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TMS320DM8168ACYG2TIN/a26avaiDaVinci Digital Media Processor 1031-FCBGA
TMS320DM8168ACYG2N/a10avaiDaVinci Digital Media Processor 1031-FCBGA


TMS320DM8168ACYG2 ,DaVinci Digital Media Processor 1031-FCBGA Features1• High-Performance DaVinci Digital Media • System Memory Management Unit (System MMU)Proce ..
TMS320DM8168ACYG2 ,DaVinci Digital Media Processor 1031-FCBGA SPRS614F–MARCH 2011–REVISED MARCH 20151.2 Applications• Video Encode, Decode, Transcode, and Trans ..
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TMS320DM8168ACYG2
DaVinci Digital Media Processor
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TMS320DM8168, TMS320DM8167
TMS320DM8165

SPRS614F –MARCH 2011–REVISED MARCH 2015
TMS320DM816x DaVinci™ Digital Media Processors Device Overview
1.1 Features
High-Performance DaVinci Digital Media • System Memory Management Unit (System MMU)
Processors – Maps C674x DSP and EMDA TCB Memory ARM® Cortex™-A8 RISC Processor Accessesto System Addresses 512KBof On-Chip Memory Controller (OCMC)• Upto 1.20 GHz
RAM– C674x™ VLIW DSP Media Controller• Upto1 GHz Manages HDVPSS and HDVICP2 Modules• Upto 8000 MIPS and 6000 MFLOPS Upto Three Programmable High-Definition Video• Fully Software-Compatible with C67x+ and Image Coprocessing (HDVICP2) EnginesC64x+™ Encode, Decode, Transcode Operations• ARM Cortex-A8 Core H.264, MPEG-2, VC-1, MPEG-4 SP and ASP– ARMv7 Architecture SGX530 3D Graphics Engine (Available Onlyon• In-Order, Dual-Issue, Superscalar Processor the DM8168 Device)Core Deliversupto30 MTriangles per Second• NEON™ Multimedia Architecture Universal Scalable Shader Engine– Supports Integer and Floating Point (VFPv3- Direct3D® Mobile, OpenGL® ES 1.1 and 2.0,IEEE754 Compliant)
OpenVG™ 1.1, OpenMax™ API Support• Jazelle® RCT Execution Environment Advanced Geometry DMA Driven Operation• ARM Cortex-A8 Memory Architecture Programmable HQ Image Anti-Aliasing– 32-KB Instruction and Data Caches Endianness– 256-KBL2 Cache ARM, DSP Instructions and Data– Little Endian– 64-KB RAM, 48-KBof Boot ROM HD Video Processing Subsystem (HDVPSS)• TMS320C674x Floating-Point VLIW DSP Two 165-MHz HD Video Capture Channels– 64 General-Purpose Registers (32-Bit) One 16-Bitor 24-Bit and One 16-Bit Channel– Six ALU (32-Bit and 40-Bit) Functional Units Each Channel Splittable Into Dual 8-Bit• Supports 32-Bit Integer, SP (IEEE Single Capture ChannelsPrecision, 32-Bit) and DP (IEEE Double Two 165-MHz HD Video Display ChannelsPrecision, 64-Bit) Floating Point One 16-Bit, 24-Bit, 30-Bit Channel and One• Supportsupto Four SP Adds Per Clock and
16-Bit ChannelFour DP Adds Every Two Clocks Simultaneous SD and HD Analog Output• Supportsupto Two Floating-Point (SPor
DP) Approximate Reciprocalor Square Root – Digital HDMI 1.3 Transmitter with PHY with
Operations Per Cycle HDCPupto 165-MHz Pixel Clock Functional Units – Three Graphics Layers IEEE Floating-Point Multiply • Dual 32-Bit DDR2 and DDR3 SDRAM Interfacesto: – Supportsupto DDR2-800 and DDR3-1600 SP→ SP Per Clock – Upto Eightx8 Devices Total Two Clocks – 2GBof Total Address Space Three Clocks Memory Manager Four Clocks • Programmable Multi-Zone Mapping Two32x32 and Multiplies
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