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TMS320DM368ZCE-TMS320DM368ZCED-TMS320DM368ZCEDF-TMS320DM368ZCEF
DaVinci Digital Media Processor
TMS320DM368
www.ti.com SPRS668C–APRIL 2010–REVISED JUNE 2011
TMS320DM368
Digital Media System-on-Chip (DMSoC)
Checkfor Samples: TMS320DM368 TMS320DM368 Digital Media System-on-Chip (DMSoC)
1.1 Features
device•
Highlights ARM926EJ-S™ Core–
High-Performance Digital Media
System-on-Chip (DMSoC) –
Support for 32-Bit and 16-Bit
(Thumb® Mode) Instruction Sets–
432-MHz ARM926EJ-S Clock Rate DSP Instruction Extensions and Single Cycle–
Two Video Image Co-processors
MAC(HDVICP, MJCP) Engines ARM® Jazelle® Technology–
Supportsa Rangeof Encode, Decode, and
Video Quality Operations –
Embedded ICE-RT Logic for Real-Time
Debug–
Video Processing Subsystem ARM9 Memory Architecture•
HW Face Detect Engine 16K-Byte Instruction Cache•
Resize Engine from 1/16xto8x 8K-Byte Data Cache•
16-Bit Parallel AFE (Analog Front-End)
Interface Upto 120 MHz –
32K-Byte RAM 4:2:2 (8-/16-bit) Interface –
16K-Byte ROM 8-/16-bit YCC and Upto 24-Bit RGB888 –
Little Endian
Digital Output •
Two Video Image Co-processors 3 DACs for HD Analog Video Output (HDVICP, MJCP) Engines Hardware On-Screen Display (OSD) –
Supporta Rangeof Encode and Decode
Operations–
Capableof 1080p 30fps H.264 video
processing –
H.264, MPEG4, MPEG2, MJPEG, JPEG,
WMV9/VC1–
Peripherals include EMAC, USB 2.0 OTG,
DDR2/NAND,5 SPIs,2 UARTs,2 •
Video Processing Subsystem
MMC/SD/SDIO, Key Scan –
Front End Provides:8 Different Boot Modes and Configurable •
HW Face Detect EnginePower-Saving Modes •
Hardware IPIPE for Real-Time Image compatible with Processing –
Resize Engine–
85ºC) –
Resize Images From 1/16xto8x –
Separate Horizontal/Vertical Output Paths •
IPIPE Interface •
Image Sensor (ISIF) Imager Interface Rate •
16-Bit Parallel AFE (Analog End) Interface Up MHz video •
Glueless Decoders •
BT.601/BT.656/BT.1120 Digital YCbCr ARM9™ (8-/16-Bit) Interface for 432-MHz •
Histogram Module
