TLE4271-2 ,Voltage Regulator5-V Low-Drop Fixed Voltage Regulator TLE 4271-2
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TLE4271-G ,5 V Low-Drop Fixed Voltage RegulatorFeatures• Output voltage tolerance £– 2%• Low-drop voltage• Integrated overtemperature protection• ..
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TLE4271-2-TLE4271-2G
Voltage Regulator
5-V Low-Drop Fixed Voltage Regulator TLE4271-2
FeaturesOutput voltage tolerance ≤ ± 2%Low-drop voltageIntegrated overtemperature protectionReverse polarity protectionInput voltage up to 42 VOvervoltage protection up to 65 V (≤ 400 ms)Short-circuit proofSuitable for use in automotive electronicsWide temperature rangeAdjustable reset and watchdog time
Functional DescriptionThe TLE4271-2 is functional and electrical identical to
the TLE4271.
The device is a 5-V low-drop fixed-voltage regulator.
The maximum input voltage is 42V (65V, ≤400ms).
Up to an input voltage of 26 V and for an output current
up to 550mA it regulates the output voltage within a% accuracy. The short circuit protection limits the output current of more than 650mA.
The IC can be switched off via the inhibit input. An integrated watchdog monitors the
connected controller. The device incorporates overvoltage protection and temperature
protection that disables the circuit at overtemperature.
Circuit DescriptionThe control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
The reset output RO is in high-state if the voltage on the delay capacitor CD is greater or
equal VUD. The delay capacitor CD is charged with the current ID for output voltages
greater than the reset threshold VRT. If the output voltage gets lower than VRT (’reset
condition’) a fast discharge of the delay capacitor CD sets in and as soon as VD gets lower
than VLD the reset output RO is set to low-level.
The time for the delay capacitor charge from VUD to VLD is the reset delay time tD.
When the voltage on the delay capacitor has reached VUD and reset was set to high, the
watchdog circuit is enabled and discharges CD with the constant current IDWD. If there is
no rising edge observed at the watchdog input, CD will be discharge down to VLDW, then
reset output RO will be set to low and CD will be charged again with the current IDWC until
VD reaches VUD and reset will be set high again.
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period CD is charged again and the reset output stays high. After VD has reached VUD,
the periodical behavior starts again.
Internal protection circuits protect the IC against:OverloadOvervoltageOvertemperatureReverse polarity
Figure2Block Diagram
Absolute Maximum Ratings Tj = – 40 to 150 °C
Input
Inhibit
Reset Output
Reset Delay
Watchdog
Output
Ground
Temperatures
Operating Range
Thermal Resistance
Characteristics =13.5 V; – 40°C≤Tj=≤125°C; VINH > VU,INH (unless otherwise specified)Drop voltage=VI–VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
Reset Generator
Overvoltage Protection
InhibitTest condition not applicable during delay time for power-on reset.
Characteristics (cont’d)=13.5 V; – 40°C≤Tj=≤125°C; VINH > VU,INH (unless otherwise specified)
Watchdog
Characteristics (cont’d)=13.5 V; – 40°C≤Tj=≤125°C; VINH > VU,INH (unless otherwise specified)
Figure3Test Circuit
Figure4Circuit
Application DescriptionThe IC regulates an input voltage in the range of 6 V < VI < 40 V to VQnom = 5.0 V. Up to
26 V it produces a regulated output current of more than 550mA. Above 26 V the save-
operating-area protection allows operation up to 36 V with a regulated output current of
more than 300mA. Overvoltage protection limits operation at 42V. The overvoltage
protection hysteresis restores operation if the input voltage has dropped below 36V. The
IC can be switched off via the inhibit input, which causes the quiescent current to drop
below 50μA. A reset signal is generated for an output voltage of VQ<4.5V. The
watchdog circuit monitors a connected controller. If there is no positive-going edge at the
watchdog input within a fixed time, the reset output is set to low. The delay for power-on
reset and the maximum permitted watchdog-pulse period can be set externally with a
capacitor.
Design Notes for External ComponentsAn input capacitor CI is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1Ω in series with CI. An output capacitor CQ is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of CQ≥22μF and an ESR ofΩ.
Reset CircuitryIf the output voltage decreases below 4.5 V, an external capacitor CD on pin D will be
discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a
reset signal is generated on pin RO, i.e. reset output is set low. If the output voltage rises
above the reset threshold, CD will be charged with constant current. After the power-on-
reset time the voltage on the capacitor reaches VDU and the reset output will be set high
again. The value of the power-on-reset time can be set within a wide range depending
of the capacitance of CD.
Reset TimingThe power-on reset delay time is defined by the charging time of an external capacitord which can be calculated as follows:D= CD∗ΔV/ID
Definitions:CD=delay capacitorD=reset delay timeD=charge current, typical 14 µA=VUD, typical 1.8VUD=upper delay timing threshold at CD for reset delay time
The reset reaction time trr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1μs
for delay capacitor of 47nF. For other values for Cd the reaction time can be estimated
using the following equation:RR≈20s/F×Cd
Figure5Time Response
