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Partno Mfg Dc Qty AvailableDescript
TLC555CDRN/A N/a1avaiLow Power Timer
TLC555IDTEXASN/a2000avaiLow Power Timer
TLC555IPN/A N/a1avaiLow Power Timer
TLC555CDTIN/a382avaiLow Power Timer
TLC555CDG4TIN/a1338avai2.1-MHz, 250-?A, Low-Power Timer 8-SOIC 0 to 70
TLC555CDG4TEXASN/a124avai2.1-MHz, 250-?A, Low-Power Timer 8-SOIC 0 to 70
TLC555CPTIN/a15890avaiLow Power Timer
TLC555CPSRTIN/a4000avaiLow Power Timer
TLC555CPWTIN/a8736avaiLow Power Timer
TLC555CPWRTIN/a9240avaiLow Power Timer
TLC555IDTIN/a2243avaiLow Power Timer
TLC555IDG4TIN/a1338avai2.1-MHz, 250-?A, Low-Power Timer 8-SOIC -40 to 85
TLC555IDRTI Pb-freeN/a2899avaiLow Power Timer
TLC555IDRG4TIN/a6500avai2.1-MHz, 250-?A, Low-Power Timer 8-SOIC -40 to 85
TLC555QDRTIN/a5000avaiLow Power Timer
TLC555QDRTI,TIN/a5000avaiLow Power Timer
TLC555QDRG4TIN/a5000avai2.1-MHz, 250-?A, Low-Power Timer 8-SOIC


TLC555CP ,Low Power TimerElectrical Characteristics: V = 5 V .... 14DD12.5 Glossary. 287.8 Typical Characteristics........ 1 ..
TLC555CPSR ,Low Power TimerFeatures... 18.3 Feature Description.... 152 Applications..... 18.4 Device Functional Modes.... 193 ..
TLC555CPW ,Low Power TimerElectrical Characteristics: V = 15 V... 11DD12.4 Electrostatic Discharge Caution. 287.7
TLC555CPWR ,Low Power TimerFeatures 3 DescriptionThe TLC555 is a monolithic timing circuit fabricated1• Very Low Power Consump ..
TLC555ID ,Low Power Timer SLFS043H–SEPTEMBER 1983–REVISED AUGUST 20165 Device Comparison TableSMALL CHIP CERAMIC PLASTICV SS ..
TLC555ID ,Low Power TimerElectrical Characteristics: V = 15 V... 11DD12.4 Electrostatic Discharge Caution. 287.7
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TLC555CD-TLC555CDG4-TLC555CDR-TLC555CP-TLC555CPSR-TLC555CPW-TLC555CPWR-TLC555ID-TLC555IDG4-TLC555IDR-TLC555IDRG4-TLC555IP-TLC555QDR-TLC555QDRG4
Low Power Timer
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TLC555

SLFS043H –SEPTEMBER 1983–REVISED AUGUST 2016
TLC555 LinCMOS™ Timer Features
Very Low Power Consumption: 1 mW Typicalat VDD=5V Capableof Operationin Astable Mode CMOS Output Capableof Swinging Railto Rail High Output Current Capability Sink: 100 mA Typical Source:10 mA Typical Output Fully Compatible With CMOS, TTL, and
MOS Low Supply Current Reduces Spikes During
Output Transitions Single-Supply Operation From2Vto15V Functionally Interchangeable With the NE555;
Has Same Pinout ESD Protection Exceeds 2000V Per MIL-STD-
883C, Method 3015.2 Availablein Q-Temp Automotive High-Reliability Automotive Applications Configuration Control and Print Support Qualificationto Automotive Standards Applications Precision Timing Pulse Generation Sequential Timing Time Delay Generation Pulse Width Modulation Pulse Position Modulation Linear Ramp Generator
Simplified Schematic Description

The TLC555isa monolithic timing circuit fabricated
using theTI LinCMOS™ process. The timeris fully
compatible with CMOS, TTL, and MOS logic, and
operatesat frequencies upto2 MHz. Becauseofits
high input impedance, this device uses smaller timing
capacitors than those used by the NE555. Asa
result, more accurate time delays and oscillations are
possible. Power consumptionis low across the full
rangeof power-supply voltage.
Like the NE555, the TLC555 hasa trigger level equal approximately one-thirdof the supply voltage anda
threshold level equalto approximately two-thirdsof
the supply voltage. These levels can be altered by
useof the control voltage terminal (CONT). When the
trigger input (TRIG) falls below the trigger level, the
flip-flopis set and the output goes high.If TRIGis
above the trigger level and the threshold input
(THRES)is above the threshold level, the flip-flopis
reset and the outputis low. The reset input (RESET)
can override all other inputs and can be usedto
initiatea new timing cycle.If RESETis low, the flip-
flopis reset and the outputis low. Whenever the
output is low,a low-impedance pathis provided
between the discharge terminal (DISCH) and GND.
All unused inputs mustbe tiedto an appropriate logic
levelto prevent false triggering.
Device Information(1)

(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
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