TLC551CDG4 ,LinCMOS(TM) Timer 8-SOIC 0 to 70maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
TLC551CP ,LinCMOS(TM) Timerelectrical characteristics.TLC551Y chip informationThis chip, when properly assembled, displays cha ..
TLC552CN ,Dual LinCMOS(TM) Timermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
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TLC5540INSR ,8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Powerblock diagramResistorReferenceOEDividerREFB270 ΩNOMLower SamplingREFTLower EncoderD1(LSB)Comparator ..
TLC5540INSRG4 ,8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Power 24-SO -40 to 85SLAS105D − JANUARY 1995 − REVISED APRIL 2004Terminal FunctionsTERMINALI/O I/O DESCRIPTION DESCRIPTI ..
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TLC551CD-TLC551CDG4-TLC551CP
LinCMOS(TM) Timer
to Rail High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ Output Fully Compatible With CMOS, TTL,
and MOS Low Supply Current Reduces Spikes
During Output Transitions Single-Supply Operation From 1 V to 15 V Functionally Interchangeable With the
NE555; Has Same Pinout ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2
descriptionThe TLC551 is a monolithic timing circuit
fabricated using the TI LinCMOSprocess. The
timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared
to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result,
more accurate time delays and oscillations are possible. Power consumption is low across the full range of
power supply voltage.
Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs
should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
The TLC551C is characterized for operation from 0°C to 70°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
LinCMOS is a trademark of .
THRES
