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TDA9102C/T
H/V PROCESSOR FOR TTL V.D.U
TDA9102C/TH/V PROCESSOR FOR TTL V .D.U
May 1994
HORIZONTAL SECTION. SYNCHRONIZATION INPUT : TTL COMPAT-
IBLE, NEGATIVE EDGE TRIGGERED. SYNCHRONIZATION INDEPENDENT FROM
DUTY CYCLE TIME. OSCILLATOR : FREQUENCY RANGE FROM
15kHz to 100kHz. HORIZONTAL OUTPUT PULSE SHAPER
AND SHIFTER. PHASE COMPARATOR BETWEEN SYN-
CHRO AND OSCILLATOR (PLL1). PHASE COMPARATOR BETWEEN FLYBACK
AND OSCILLATOR (PLL2). INTERNAL VOLTAGE REGULATOR. DC COMPATIBLE CONTROLS FOR PHASE
AND FREQUENCY. HORIZONTAL OUTPUT DUTY CYCLE : 41%
VERTICAL SECTION. SYNCHRONIZATION INPUT : TTL COMPAT-
IBLE, NEGATIVE EDGE TRIGGERED. SYNCHRONIZATION INDEPENDENT FROM
DUTY CYCLE TIME. OSCILLATOR : FREQUENCY RANGE FROM
30Hz to 120Hz. RAMP GENERATOR WITH VARIABLE GAIN
STAGE. VERTICAL RAMP VOLTAGE REFERENCE. INTERNAL VOLTAGE REGULATOR. DC COMPATIBLE CONTROLS FOR FRE-
QUENCY, AMPLITUDE AND LINEARITY
DESCRIPTIONThe TDA9102C/T is a monolithic integrated circuit
for horizontal and vertical sync processing in mono-
chrome and color video displays driven by input
TTL compatible signals.
The TDA9102C/T is supplied in a 20 pin dual in line
package with pin 11 connected to ground and used
for heatsinking.
PIN CONNECTIONS1/7
BLOCK DIAGRAM
TDA9102C/T2/7
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
ELECTRICAL CHARACTERISTICS(Tamb = 25o C, VS = 12V, refer to the test circuits, unless otherwise specified)
HORIZONTAL SECTION
TDA9102C/T3/7
ELECTRICAL CHARACTERISTICS (continued)(Tamb = 25o C, VS = 12V, refer to the test circuits, unless otherwise specified)
HORIZONTAL SECTION
VERTICAL SECTION
TDA9102C/T4/7
ELECTRICAL CHARACTERISTICS (continued)(Tamb = 25o C, VS = 12V, refer to the test circuits, unless otherwise specified)
VERTICAL SECTION
Technical note 1fH (nom) = 26.8 kHz
R1 = 6.8k Ω
R2 = 56 kΩ
C2 = 1.8 nF
fpull-in = fH (nom) V3 − V1 / R2
V1 / R1 = fH (nom) If (A)
where: V1 = 3.5V and V3 - V1 is the control
voltage range.
The voltage at Pin 3 is limited by two clamping
diodes at the voltage V3H and V3L
When the PLL1 is synchronized and perfectly
tuned, V3 = V1.
Remark: The value of C2 influences the horizontaloscillator free running frequency; it doesn’t effect
the relative pull-in range. If the horizontal fre-
quency is changed by using R1, the pull-in range
changes accordingly with the formula (A).
Technical note 2The internal pulse "t5", is generated by the current
generator "I5" charging the external capacitor
"C5", according with the formula (B):
t5 = C5 . V5 (B), t5 = TH is recommended.
Technical note 3K9 = 67.5 degrees/volt represents the slope of the
oscillator charging period of the waveform at
Pin 2:
K9 = 360 x 0.75 degree
Technical note 4The second PLL can recover the storage of hori-
zontal output stage maintaining a constant duty
cycle till the trailing edge of the output pulse gets
the trailing edge of the flyback pulse. From this
point on, only the leading edge of the output pulse
will be shifted covering a total phase shift of: 0.30T;
overcoming this value, it will produce a notch in the
output pulse (@ fH = 27kHz).
Technical note 5The voltage reference at Pin 19 can be used to
polarize the DC operating point of the vertical
booster. This voltage corresponds to the double of
the mean value voltage of the vertical sawtooth at
Pin 13.
Technical note 6VH − VL = VH − VLL
1/fV
ts = (VH − VL)
(VH − VLL) 1 = K14
TDA9102C/T5/7
APPLICATION DIAGRAM (with TDA8172)
TDA9102C/T6/7
