TDA8204B ,NICAM DECODERTDA8204BNICAM DECODER.HIGHLY INTEGRATED TWO-CHIP SOLU-TION FOR NICAM DEMODULATION (usingTDA8205 QSP ..
TDA8204B ,NICAM DECODERELECTRICAL CHARACTERISTICS (T = 25 C, V = 5V, unless otherwise specified)amb DDSymbol Parameter Mi ..
TDA8205 ,NICAM QPSK demodulatorTDA8205NICAM QPSK DEMODULATOR.HIGHLY INTEGRATED TWO CHIP SOLU-TION FOR NICAM DEMODULATION (usingTDA ..
TDA8213 ,VIDEO & SOUND IF SYSTEMTDA8213VIDEO & SOUND IF SYSTEM.VERY LOW CURRENT ABSORPTION.3 STAGE IF GAIN CONTROLLED AMPLIFIER.SYN ..
TDA8214 ,HORIZONTAL AND VERTICAL DEFLECTION CIRCUITELECTRICAL CHARACTERISTICS oVCC1 = 10V, TAMB = 25 C (unless otherwise specified )Symbol Parameter M ..
TDA8214B ,HORIZONTAL AND VERTICAL DEFLECTION CIRCUITABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV 1 Supply Voltage 30 VCCVCC2 Flyback Generator ..
TIBPAL16L8--10MJB ,High-Performance Impact-X<TM> PAL<R> Circuits 20-CDIP -55 to 125
TIBPAL16L8-15MJB ,High-Performance Impact<TM> PAL<R> Circuits 20-CDIP -55 to 125TIBPAL16L8-15M is Not Recommended for New DesignsTIBPAL16L8-15M, TIBPAL16R4-15M®HIGH-PERFORMANCE IM ..
TIBPAL16L8-15MJB ,High-Performance Impact<TM> PAL<R> Circuits 20-CDIP -55 to 125TIBPAL16L8-15M is Not Recommended for New DesignsTIBPAL16L8-15M, TIBPAL16R4-15M®HIGH-PERFORMANCE IM ..
TIBPAL16L8--15MJB ,High-Performance Impact<TM> PAL<R> Circuits 20-CDIP -55 to 125block diagrams (positive logic)TIBPAL16L8’& ≥1ENO732 X 64O716 x I/O710 16I7 I/OI/O76 16I/O7I/O7I/O7 ..
TIBPAL16L8-20MWB ,High-Performance Impact<TM> PAL<R> Circuits 20-CFP -55 to 125block diagrams (positive logic)TIBPAL16L8’≥ 1&ENO732 × 64O716 ×I/O710 16II/O77 I/O6 16I/O7I/O7I/O76 ..
TIBPAL16L8-25CFN , LOW-POWER HIGH-PERFORMANCE IMPACT E PAL CIRCUITS
TDA8204B
NICAM DECODER
TDA8204BNICAM DECODER
November 1994
PIN CONNECTIONS HIGHLY INTEGRATED TWO-CHIP SOLU-
TION FOR NICAM DEMODULATION (using
TDA8205 QSPK). DATA AND SOUND RECOVERY ACCORDING
TO EBU SPB 424 SPECIFICATIONS.I2S INTERFACE FOR DIGITAL AUDIO PUR-
POSES (14-bit samples, 32kHz word select
clock, 896kHz serial clock).4 TIMES UP SAMPLING DIGITAL FILTER
AND NOISE SHAPER.I2C INTERFACE FOR MICROCONTROLLER
SOFTWARE DRIVE. PAY TV APPLICATION CAPABILITIES. AUTOMATIC ERROR MONITORING
(programmable error rate limit)
DESCRIPTIONThe TDA8204B performs two main functions, first
one is NICAM decoding, second one is audio signal
recovery (DAC) combined with audio signal switch-
ing (Matrix). An I2S output is provided for digital
audio when required and all functions of both the
TDA8204B and the TDA8205 are accessed via an
on-chip I2 C bus interface. The I2 S interface can be
used as an input for converting to analog some I2S
digital sound.
1/12
PIN ASSIGMENT
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
TDA8204B2/12
ELECTRICAL CHARACTERISTICS (Tamb = 25o C, VDD = 5V , unless otherwise specified)
SUPPLY
OUTPUTS
INPUTS
BI-DIRECTIONAL2 C INTERFACE
TDA8204B3/12
ELECTRICAL CHARACTERISTICS (continued)2 C BUS TIMING
Figure 1 : I2 C Serial Bus Timing
Figure 2 : I2 S Bus Timing Diagram
TDA8204B4/12
Figure 3 : NICAM Decoder Block Diagram
FUNCTION DESCRIPTIONThe TDA8204B is partitioned into 6 major parts
shown in the block diagram.
The NICAM Decoder performs data and sound covery from the signals specified in
EBU SPB 424. The expanded digital audio signals
(14-bit) are made available at the digital audio
interface (I2 S) in a serial multiplex of left and right
channels. They are also processed by a 4 times
upsampling digital filter and noise shaper which
results in a high speed digital data stream at the
output pins DACDL/DACDR. This data stream can
be applied to the 1-bit D-A convertors contained in
the TDA8205.
The TDA8204B is I2 C bus controlled and provides
control over the functions of the TDA8205 by
means of a serial inter-chip bus.
1 - NICAM Decoder1.1 - BLOCK DIAGRAM (see Figure 3)
1.2 - DESCRIPTION
NICAM frame alignment requires searching out a
frame alignment word (FAW) and a 16 frame se-
quence conveyed by C0 bit. Because of noise,
interferences, errors in the incoming NICAM Data,
aliases of the FAW, a robust scheme is imple-
mented. It ensures the decoder will align, and stay
aligned, to signals beyond the limit of maximum
useable error rate. Thanks to a 511 bit PRBS syn-
chronized by the recovered clock and a modulo 2
adder, original data are recovered. This data
stream can be processed externaly for de-encryp-
tion in Pay TV applications using descrambled data
Pins DDO, DDI.
To allow simultaneous reading and writing of
mono/stereo samples, de-interleaved data frames
are stored in a 3 page RAM.
The 10-bit input audio samples are expanded to
14-bit using scale factor bits according to NICAM
decoding rules. Samples in error by the parity
check are replaced by interpolated one or re-
peated.
Mute is set according to an error counter when the
error rate exceeds error rate limit (ERL) and reset
when the error rate is below ERL/4.
Application control information (bit C1, C2, C3, C4)
is recovered by majority decision logic over 16
frames. the C1, C2, C3 , C4 bits can be read in SR0
register and are set on the C1, C2, C3, C4 pins
according to the state of bit 0 (BEA) of the CR2
register.
2 - Digital Filter and Noise Shaper digital filter performs 4X upsampling in two
stages. The main FIR 2x upsampler is followed by
a smaller 2x FIR upsampler. Digital upsampling
means a much simpler post-DAC reconstruction
filter can be used thus saving on external compo-
nent count and cost. noise shaper converts the samples from the
digital filter into two high speed serial bitstreams
which can be applied to the DACs in the TDA8205.
3 - I2 S BusA standard three-wire interface, conforming to the2 S bus protocol, is provided, allowing connection
of an external DAC or DAT interface. Audio samples
contain 14-bit, so 16-bit DACs will pad the two LSBs
with 0. The word select clock operates at 32kHz
and the serial clock at 896kHz.
By setting SDI bit of CR2 to 1, the I2 S interface can
receive the digital I2 S sound. This prevents dupli-
cating the dual D/A converter.
TDA8204B5/12
4 - Interchip BusA one-line serial bus provides interchip communi-
cations allowing control of all functions through the
single I2 C bus interface.
5 - I2 C BusAn I2 C bus interface provides access to control and
status registers within the two chips to allow control
of their functions and monitoring of status. A digital
filter is included to improve noise immunity.
5.1 - DATA FLAGS (see Figure 4)
These indicate the status of the descrambled data
on the DDO pin. They are inhibited if the decoder
is out of alignement. FID : Frame alignment word (scrambled) PDV : Parity Data Valid. CIB0 and CIB1 overwrite
the first 2 bits of FAW ADV : 11 additional data bits DV : Data valid (mode dependant)
5.2 - DECRYPTION (see Figure 5)
The PRBS generator (used for descrambling) is
normally preset to all ones at the start of each
frame. However, it is possible to preset it to any
value on each frame by means of a code word clock
(CWC) and serial code word data (CWD) interface
on pins SEL0 and SEL1.
CWD, which is clocked in on the negative going
edges of the CWC clock, can be sent anywhere
during the frame except when FID = 1. The CWC
is asynchronous with respect to the Nicam clock
and the CWD will be used on the following frame.
During the time FID = 1, the levels on the SEL0,
SEL1 pins are read for language selection. Code
words for descrambler presetting may be sent in
either an 8-bit or 9-bit formats. There are four
possibilities : if 7 or less clock cycles are counted on CW-clock
during a frame, the PRBS generator is preset to
all ones ; if 8 clock cycles are counted, 8 bits of CW-data
are clocked into the shift register, the first bit of the
previous transfer now moving to bit 9 position in
the shift register. The resulting value is used to
preset the PRBS generator on the next frame. if 9 clock cycles are counted, the CW-data (which
has been clocked into a 9-bit shift register) is used
to preset the PRBS generator on the next frame. if 10 or more clock cycles are counted, only the
first 9 bits of the CW-data are used and loaded
into the PRBS generator on the next frame.
Figure 4 : Data Flags
Figure 5 : PRBS Presetter
TDA8204B6/12
