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TDA8029PHIN/a19avaiLow power single card reader
TDA8029HLPHILIPSN/a850avaiLow power single card reader


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TDA8029-TDA8029HL
Low power single card reader

Philips Semiconductors Product specification
Low power single card reader TDA8029
CONTENTS
FEATURES GENERAL DESCRIPTION APPLICATIONS QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
8.1 Microcontroller
8.1.1 Port characteristics
8.1.2 Oscillator characteristics
8.1.3 Reset
8.1.4 Low power modes
8.2 Timer 2 operation
8.2.1 Timer/counter 2 Control register (T2CON)
8.2.2 Timer/counter 2 Mode control register
(T2MOD)
8.2.3 Auto-reload mode (up- or down-counter)
8.2.4 Baud rate generator mode
8.2.5 Timer/counter 2 set-up
8.3 Enhanced UART
8.3.1 Serial port Control register (SCON)
8.3.2 Automatic address recognition
8.4 Interrupt priority structure
8.4.1 Interrupt Enable (IE) register
8.4.2 Interrupt Priority (IP) register
8.4.3 Interrupt Priority High (IPH) register
8.5 Dual Data Pointer (DPTR)
8.6 Expanded data RAM addressing
8.6.1 Auxiliary Register (AUXR)
8.7 Reduced EMI mode
8.8 Mask ROM devices
8.9 ROM code submission for 16 kbytes ROM
device TDA8029
8.10 Smart card reader control registers
8.10.1 General registers
8.10.1.1 Card Select Register (CSR)
8.10.1.2 Hardware Status Register (HSR)
8.10.1.3 Time-Out Registers (TOR1, TOR2 and TOR3)
8.10.1.4 Time-Out Configuration register (TOC)
8.10.2 ISO UART registers
8.10.2.1 UART Transmit Register (UTR)
8.10.2.2 UART Receive Register (URR)
8.10.2.3 Mixed Status Register (MSR)
8.10.2.4 FIFO Control Register (FCR)
8.10.2.5 UART Status Register (USR)
8.10.3 Card registers
8.10.3.1 Programmable Divider Register (PDR)
8.10.3.2 UART Configuration Register 2 (UCR2)
8.10.3.3 Guard Time Register (GTR)
8.10.3.4 UART Configuration Register 1 (UCR1)
8.10.3.5 Clock Configuration Register (CCR)
8.10.3.6 Power Control Register (PCR)
8.10.4 Register summary
8.11 Supply
8.12 DC/DC converter
8.13 ISO 7816 security
8.14 Protections and limitations
8.15 Power reduction modes
8.16 Activation sequence
8.17 Deactivation sequence LIMITING VALUES HANDLING THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING
15.1 Introduction to soldering surface mount
packages
15.2 Reflow soldering
15.3 Wave soldering
15.4 Manual soldering
15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
Philips Semiconductors Product specification
Low power single card reader TDA8029 FEATURES 80C51 core with 16 kbytes ROM, 256 bytes RAM and
512 bytes XRAM Specific ISO7816 UART, accessible with MOVX
instructions for automatic convention processing,
variable baud rate, error managementat character level
for T= 0 and T= 1 protocols, extra guard time, etc. Specific versatile 24-bit Elementary Time Unit (ETU)
counter for timing processing during Answer To Reset
(ATR) and for T= 1 protocol VCC generation (5V±5 % or 3V±5 % or 1.8 V),
maximum current 65 mA with controlled rise and fall
times Card clock generation up to 20 MHz with three times
synchronous frequency doubling (fXTAL,1 /2fXTAL,1 /4fXTAL
and1 /8fXTAL) Card clock stop HIGH or LOW or 1.25 MHz from an
integrated oscillator for card power reduction modes Automatic activation and deactivation sequences
through an independant sequencer Supports asynchronous protocols T= 0 and T= 1 in
accordance with: ISO 7816 and EMV 3.1.1 (TDA8029HL/C1 and
TDA8029HL/C2) ISO 7816 and EMV 2000 (TDA8029HL/C2).1to 8 characters FIFO in reception mode Parity error counter in reception mode and in
transmission mode with automatic retransmission Versatile 24-bit time-out counter for ATR and waiting
times processing Specific ETU counter for Block Guard Time (BGT)
(22 ETU in T= 1 and 16 ETU in T=0) Minimum delay between two characters in reception
mode: In protocol T=0: ETU (TDA8029HL/C1)
11.8 ETU (TDA8029HL/C2). In protocol T=1: ETU (TDA8029HL/C1)
10.8 ETU (TDA8029HL/C2). Supports synchronous cards which do not use C4/C8 Current limitations on card contacts Supply supervisor for power-on/off reset and spikes
killing DC/DC converter (supply voltage from 2.7to6 V),
doubler, tripler or follower according to VCC and VDD Shut-down input for very low power consumption Enhanced ESD protection on card contacts (6kV
minimum) Software library for easy integration Communication with the host through a standard full
duplex serial link at programmable baud rates One external interrupt input and four general purpose
I/Os. GENERAL DESCRIPTION
The TDA8029isa complete one chip, low cost, low power,
robust smart card reader. Its different power reduction
modes and its wide supply voltage range allow its use in
portable equipment. Dueto specific versatile hardware,a
small embedded software program allows the control of
most cards available in the market. The control from the
host may be done through a standard serial interface.
The TDA8029 maybe delivered with standard embedded
software, or be masked with specific customer code. For
details on software development and on available tools,
please refer to application notes “AN01009” and
“AN10134” for the TDA8029HL/C1. For standard
embedded software, please refer to application note
“AN10206” for the TDA8029HL/C2. APPLICATIONS Portable card readers General purpose card readers EMV compliant card readers.
Philips Semiconductors Product specification
Low power single card reader TDA8029 QUICK REFERENCE DATA
Philips Semiconductors Product specification
Low power single card reader TDA8029 ORDERING INFORMATION BLOCK DIAGRAM
Philips Semiconductors Product specification
Low power single card reader TDA8029 PINNING
Philips Semiconductors Product specification
Low power single card reader TDA8029 FUNCTIONAL DESCRIPTION
Throughout this specification,itis assumed that the reader
is aware of ISO7816 norm terminology.
8.1 Microcontroller

The embedded microcontroller is an 80C51FB with
internal 16 kbytes ROM, 256 bytes RAM and 512 bytes
XRAM. It has the same instruction set as the 80C51.
The controller is clocked by the frequency present on pin
XTAL1.
The controller may be reset by an active HIGH signal on
pin RESET, butitis also resetby the Power-on reset signal
generated by the supply supervisor.
The external interrupt INT0_N is used by the ISO UART, the analog drivers and the ETU counters.It mustbe left
open in the application.
The second external interrupt INT1_N is available for the
application.
A general description as well as added features are
described in this chapter.
The added features to the 80C51 controller are similar to
the 8XC51FB controller, except on the wake-up from
Power-down mode, whichis possiblebya falling edgeon
INT0_N (card reader problem)oron INT1_Noron RX due
to the addition of an extra delay counter and enable
configuration bits within register UCR2 (see detailed
description in Section 8.10.3.2). For any further
information please refer to the published specification of
the 8XC51FBin “Data Handbook IC20; 80C51-Based 8-bit
Microcontrollers”.
The controller has four 8-bit I/O ports, three 16-bit
timer/event counters, a multi-source, four-priority-level,
nestedinterrupt structure,an enhancedUART and on-chip
oscillator and timing circuits. For systems that require
extra memory capability up to 64 kbytes, it can be
expanded using standard TTL-compatible memories and
logic.
Philips Semiconductors Product specification
Low power single card reader TDA8029
Additional features of the controller are: 80C51 central processing unit Full static operation Security bits: ROM 2 bits Encryption array of 64 bits 4-level priority structure6 interrupt sources Full-duplex enhanced UART with framing error
detection and automatic address recognition Power control modes; clock can be stopped and
resumed, Idle mode and Power-down mode Wake-up from Power-downby falling edgeon INT0_N,
INT1_N and RX with an embedded delay counter Programmable clock out Second DPTR register Asynchronous port reset Low EMI by inhibit ALE.
Table 1 gives a list of main features to get a better
understanding of the differences between a standard
80C51, an 8XC51FB and the embedded controller in the
TDA8029.
Table 2 shows an overview of the special function
registers.
Table 1
Principal blocks in 80C51, 8XC51FB and TDA8029
Philips Semiconductors Product specification
Low power single card reader TDA8029
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le 2

Embedded controller Special Function Registers (SFRs)
Philips Semiconductors Product specification
Low power single card reader TDA8029
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Notes 1.
Register is bit addressable.
Register is modified from or added to the 80C51 SFRs.
Reset value depends on reset source.
Bit will not be affected by reset.
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.1.1 PORT CHARACTERISTICS
Port 0 (P0.7
to P0.0): Port 0 is an open-drain,
bidirectional, I/O timer 2 generated commonly used baud
rates port. Port 0 pins that have logic 1s written to them
float and canbe usedas high-impedance inputs. Port0is
also the multiplexed low-order address and data bus
during access to external program and data memory. this application, it uses strong internal pull-ups when
emitting logic 1s. Port0 also outputs the codebytes during
program verification and received code bytes during
EPROM programming. External pull-ups are required
during program verification.
Port 1 (P1.7
to P1.0): Port 1 is an 8-bit bidirectional
I/O-port with internal pull-ups. Port 1 pins that have
logic 1s written to them are pulled to HIGH level by the
internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled LOW will source
current because of the internal pull-ups. Port 1 also
receives the low-order address byte during program
memory verification. Alternate functionsfor port1 include: T2 (P1.0): Timer/counter 2 external count input / clock
out (see programmable clock out) T2EX (P1.1): Timer/counter 2 reload/capture/direction
control.
Port 2 (P2.7
to P2.0): Port 2 is an 8-bit bidirectional I/O
port with internal pull-ups. Port 2 pins that have logic1s
written to them are pulled to HIGH level by the internal
pull-ups and canbe usedas inputs.As inputs, port2 pins
that are externally being pulledto LOW will source current
because of the internal pull-ups. Port 2 emits the
high-order address byte during fetches from external
program memory and during access to external data
memory that use 16-bit addresses (MOVX @DPTR). In
this application, it uses strong internal pull-ups when
emitting logic 1s. During access to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the
contents of the P2 special function register. Some port2
pins receive the high order address bits during EPROM
programming and verification.
Port 3 (P3.7
to P3.3, P3.1 and P3.0): Port 3 is a 7-bit
bidirectional I/O port with internal pull-ups. Port3 pins that
have logic 1s written to them are pulled to HIGH level by
the internal pull-ups and canbe usedas inputs.As inputs,
port3 pinsthat areexternally being pulled LOW will source
current because of the pull-ups.
Port3 also serves the special featuresof the 80C51 family: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 (pin INT0_N) INT1 (P3.3): External interrupt 1 (pin INT1_N T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe.
8.1.2 OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier. The pins can be configured for
use as an on-chip oscillator. To drive the device from an
external clock source, XTAL1 should be driven while
XTAL2is left unconnected. There areno requirementson
the duty cycle of the external clock signal, because the
input to the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum and maximum
HIGH and LOW times specified must be observed.
8.1.3 RESET
The microcontrolleris reset when the TDA8029is reset,as
described in Section 8.11.
8.1.4 LOW POWER MODES
This section describes the low power modes of the
microcontroller. Please referto Section 8.15for additional
information of the TDA8029 power reduction modes.
Stop clock mode: The static design enables the clock

speedtobe reduced downto0 MHz (stopped). When the
oscillator is stopped, the RAM and special function
registers retain their values. This mode allows
step-by-step utilization and permits reduced systempower
consumptionby lowering the clock frequency downto any
value. For lowest power consumption the Power-down
mode is suggested.
Idle mode: In the Idle mode, the CPU puts itself to sleep

while all of the on-chip peripherals stay active. The
instruction to invoke the Idle mode is the last instruction
executed in the normal operating mode before the Idle
mode is activated. The CPU contents, the on-chip RAM,
andallof the special function registers remain intact during
Philips Semiconductors Product specification
Low power single card reader TDA8029
this mode. The Idle mode canbe terminated eitherby any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
Power-down mode: To save even more power, a

Power-down mode can be invoked by software. In this
mode, the oscillator is stopped and the instruction that
invoked Power-down is the last instruction executed.
Either a hardware reset, external interrupt or reception RX canbe usedto exit from Power-down mode. Reset
redefines all the SFRs but does not change the on-chip
RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
With INT0_N, INT1_Nor RX, the bitsin registerIE mustbe
enabled. Within the INT0_N interrupt service routine, the
controller has to read out the Hardware Status Register
(HSR@ 0Fh) and/or the UART Status register
(USR@ 0Eh)by meansof MOVX-instructionsin orderto
know the exact interrupt reason and to reset the interrupt
source.
For enablinga wakeupby INT1_N, thebit ENINT1 within
UCR2 must be set.
For enablinga wakeupby RX, the bits ENINT1 and ENRX
within UCR2 must be set.
An integrated delay counter maintains internally INT0_N
and INT1_N LOW long enough to allow the oscillator to
restart properly,soa falling edgeon pins RX, INT0_N and
INT1_N is enough for awaking the whole circuit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the
instruction that put the device into power-down.
Table 3
External pin status during Idle and Power-down mode
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.2 Timer 2 operation

Timer2isa 16-bit timer and counter which can operateas eitheran event timeroran event counter,as selectedbybit
C/T2 in the special function register T2CON. Timer 2 has three operating modes: capture, auto-reload (up-or down
counting), and baud rate generator, which are selected by bits in register T2CON.
8.2.1 TIMER/COUNTER 2CONTROL REGISTER (T2CON)
Table 4
Timer/counter 2 control register bits
Table 5
Description of register bits
Table 6
Timer 2 operating modes
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.2.2 TIMER/COUNTER 2MODE CONTROL REGISTER (T2MOD)
Table 7
Timer/counter 2 mode control register bits
Table 8
Description of register bits
Note
Do not write logic1sto reserved bits. These bits maybe usedin future 80C51 family productsto invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.2.3 AUTO-RELOAD MODE (UP-OR DOWN-COUNTER) the 16-bit auto-reload mode, timer2 canbe configured
as either a timer or counter (bit C/T2 in register T2CON)
and programmed to count up or down. The counting
direction is determined by bit DCEN (down-counter
enable) which is located in the T2MOD register. When
reset, DCEN= 0 and timer 2 will default to counting up. If
DCEN=1, timer2 can countupor down dependingon the
value of T2EX.
When DCEN= 0, timer 2 will count up automatically. this mode there are two options selectedbybit EXEN2 register T2CON.If EXEN2=0, thentimer2 countsupto
0FFFFh and sets the TF2 overflow flag upon overflow.
This causes the timer 2 registers to be reloaded with the
16-bit value in RCAP2L and RCAP2H. The values in
RCAP2L and RCAP2H are preset by software. If
EXEN2=1, thena 16-bit reload canbe triggered eitherby
an overflow or by a HIGHto LOW transition at controller
input T2EX. This transition also sets the EXF2 bit. The
timer2 interrupt,if enabled, canbe generated when either
TF2 or EXF2 are logic 1. See Fig.3 for an overview.
DCEN= 1 enables timer 2 to count up- or down. This
mode allows T2EXto control the directionof count. When
a HIGH level is applied at T2EX timer 2 will count up.
Timer 2 will overflow at 0FFFFh and set the TF2 flag,
which can then generate an interrupt, if the interrupt is
enabled. This timer overflow also causes the 16-bit value
in RCAP2L and RCAP2H to be reloaded into the timer
registers TL2 and TH2. When a LOW level is applied at
T2EX this causes timer 2 to count down. The timer will
underflow when TL2 and TH2 become equal to the value
stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 overflow flag and causes 0FFFFhtobe reloaded
into the timer registers TL2 and TH2. See Fig.4 for an
overview.
The external flag EXF2 toggleswhen timer 2underflowsor
overflows. This EXF2 bit can be used as a 17th bit of
resolutionif needed. The EXF2 flag does not generatean
interrupt in this mode of operation.
Philips Semiconductors Product specification
Low power single card reader TDA8029
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.2.4 BAUD RATE GENERATOR MODE
Bits TCLK and/or RCLKin register T2CON allow the serial
port transmit and receive baud rates to be derived from
either timer1or2. When TCLK=0, timer1is usedas the
serial port transmit baud rate generator. When TCLK=1,
timer 2 is used. RCLK has the same effect for the serial
port receive baud rate. With these two bits, the serial port
can have different receive and transmit baud rates, one
generated by timer 1, the other by timer2.
The baud rate generation mode is like the auto-reload
mode,in thata rolloverin TH2 causes the timer2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.
The baud rates in modes 1 and 3 are determined by the
overflow rate of timer 2, given by equation (1):
(1)
The timer can be configured for either timer or counter
operation. In many applications, it is configured for timer
operation (C/T2= 0). Timer operation is different for
timer 2 when it is being used as a baud rate generator.
Usually,asa timerit would increment every machine cycle
(i.e.1/12 fosc). Asa baudrate generator,it increments every
state time (i.e.1 /2fosc). Thus the modes1 and3 baud rate
formula is as Equation (2):
(2)
Where (RCAP2H, RCAP2L) is the contents of RCAP2H
and RCAP2L registers takenasa 16-bit unsigned integer.
The timer 2 as a baud rate generator is valid only if
RCLK= 1 and/or TCLK= 1 in the T2CON register. Note
that a rollover in TH2 does not set TF2, and will not
generatean interrupt. Thus, the timer2 interrupt does not
have to be disabled when timer 2 is in the baud rate
generator mode. Also if the EXEN2 (T2 external enable)
flag is set, a HIGH to LOW transition on T2EX
(Timer/counter 2 trigger input) will set the EXF2 (T2
external) flag but will not cause a reload from (RCAP2H
and RCAP2L)to (TH2 and TL2). Therefore, when timer2 usedasa baud rate generator, T2EX canbe usedasan
additional external interrupt, if needed.
When timer2isin the baud rate generator mode, nevertry
to read or write TH2 and TL2. As a baud rate generator,
timer 2 is incremented every state time (1 /2fosc) or
asynchronously from controller I/O T2; under these
conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should
not be written to, because a write might overlap a reload
and cause write and/or reload errors. The timer shouldbe
turned off (clear TR2) before accessing the timer 2 or
RCAP2 registers. See Fig.5 for an overview.
Baud rate Timer 2 overflow rate --------------------------------------------------------=
Baud rate Oscillator frequency 65536 RCAP2H, RCAP2L()– []× ------------------------------------------------------------------------------------------------=
Table 9
Timer 2 generated commonly used baud rates
Philips Semiconductors Product specification
Low power single card reader TDA8029
Summary of baud rate equations: Timer 2 is in baud rate
generating mode. If timer 2 is being clocked through T2
(P1.0) the baud rate is:
(3)
If timer 2 is being clocked internally, the baud rate is:
(4) obtain the reload valuefor RCAP2H and RCAP2L, the
above equation can be rewritten as:
(5)
Where fosc= oscillator frequency.
Baud rate Timer 2 overflow rate --------------------------------------------------------=
Baud rate Oscillator frequency 65536 RCAP2H, RCAP2L()– []× ------------------------------------------------------------------------------------------------=
RCAP2H, RCAP2L 65536 fosc baud rate× --------------------------------------–=
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.2.5 TIMER/COUNTER2 SET-UP
Exceptfor the baud rate generator mode, the values givenfor T2CONdo not include the settingof the TR2 bit.Therefore,
bit TR2 must be set, separately, to turn the timer on.
Table 10
Timer 2 as a timer
Notes
Capture/reload occurs only on timer/counter overflow. Capture/reloadon timer/counter overflow anda HIGHto LOW transitionon T2EX, except when timer2is usedin the
baud rate generator mode.
Table 11
Timer 2 as a counter
Notes
Capture/reload occurs only on timer/counter overflow. Capture/reloadon timer/counter overflow anda HIGHto LOW transitionon T2EX (P1.1) pin except when timer2is
used in the baud rate generator mode.
8.3 Enhanced UART

The UART operates in all of the usual modes that are described in the first section of “Data Handbook IC20,
80C51-based 8-bit microcontrollers”. In addition the UART can perform framing error detection by looking for missing
stop bits and automatic address recognition. The UART also fully supports multiprocessor communication as does the
standard 80C51 UART.
When usedfor framing error detection the UART looksfor missing stop bitsin the communication.A missingbit will set
thebitFEorbit7in the SCON register.Bit FEis shared withbit SM0. The functionof SCONbit7is determinedbybit6 register PCON (bit SMOD0).If SMOD0is set thenbit7of register SCON functionsas FE andas SM0 when SMOD0
is cleared. When used as FE this bit can only be cleared by software.
8.3.1 SERIAL PORT CONTROL REGISTER (SCON)
Table 12
Serial port control register bits
Philips Semiconductors Product specification
Low power single card reader TDA8029
Table 13
Description of register bits
Table 14
Enhanced UART modes
8.3.2 AUTOMATIC ADDRESS RECOGNITION
Automatic address recognition is a feature which allows
the UART to recognize certain addresses in the serial bit
streamby using hardwareto make the comparisons. This
feature saves a great deal of software overhead by
eliminating the need for the software to examine every
serial address which passesby the serial port. This feature enabledby setting the SM2bitin register SCON.In the
9-bit UART modes (modes2 and3), the Receive Interrupt
flag (RI) will be automatically set when the received byte
contains either the ‘given’ address or the ‘broadcast’
address. The 9-bit mode requires that the 9th information
bitisa logic1to indicate that the received informationisan
address and not data. Figure 7 gives a summary.
The 8-bit mode is called mode 1. In this mode the RI flag
willbe setif SM2is enabled and the information received
has a valid stop bit following the 8 address bits and the
information is either a given or a broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the automatic address recognition feature allows a
master to selectively communicate with one or more
slavesby invoking the given slave addressor addresses.
Allof the slaves maybe contactedby using the broadcast
Philips Semiconductors Product specification
Low power single card reader TDA8029
address. Two special function registers are usedto define
the slave addresses, SADDR, and the address mask,
SADEN. SADENis usedto define which bitsin the SADDR
are to be used and which bits are ‘don’t cares’. The
SADEN mask canbe logically AND-ed with the SADDRto
create the given address which the master will use for
addressing each of the slaves. Use of the given address
allows multiple slaves to be recognized while excluding
others. The following examples will help to show the
versatility of this scheme.
Table 15
Slave0
Table 16
Slave1 the above example SADDRis the same and the SADEN
data is used to differentiate between the two slaves.
Slave 0 requires that bit0= 0 and ignores bit 1. Slave1
requires that bit1= 0 and bit 0 is ignored. A unique
address for slave 0 would be 1100 0010 since slave1
requires bit1= 0. A unique address for slave 1 would be
1100 0001 sincebit0=1 will exclude slave0. Both slaves
canbe selectedat the same timebyan address which has
bit0=0 (for slave0) and bit1=0 (for slave1). Thus, both
could be addressed with 1100 0000.
In a more complex system the following could be used to
select slaves 1 and 2 while excluding slave0.
Table 17
Slave0
Table 18
Slave1
Table 19
Slave2
In the above example the differentiation among the slaves is in the lower 3 address bits. Slave 0 requires
that bit0=0 and it can be uniquely addressed by
1110 0110. Slave 1 requires that bit1=0 and it can be
uniquely addressed by 1110 and 0101. Slave 2 requires
that bit2=0 and its unique address is 1110 0011. select slaves0 and1 and exclude slave2 use address
1110 0100, since it is necessary to make bit2= 1 to
exclude slave2.
The broadcast addressfor each slaveis createdby taking
the logical ORof SADDR and SADEN. Zerosin this result
are treatedas don’t cares.In most cases, interpreting the
don’t cares as ones, the broadcast address will be FFh.
Upon reset SADDR (SFR address 0A9h) and SADEN
(SFR address 0B9h) are leaded with 0s. This produces a
given address of all ‘don’t cares’ as well as a broadcast
address of all ‘don’t cares’. This effectively disables the
automatic addressing mode and allows the microcontroller
to use standard 80C51 type UART drivers which do not
make use of this feature.
Philips Semiconductors Product specification
Low power single card reader TDA8029
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.4 Interrupt priority structure

The TDA8029 has a 6-source 4-level interrupt structure.
There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt Priority High (IPH) register
implements the 4-level interrupt structure. The IPH is located at SFR address B7h.
The functionof the IPHis simple and when combined with theIP determines the priorityof each interrupt. The priorityof
each interrupt is determined as shown in Table 20.
Table 20
Priority bits
Table 21
Interrupt table
Notes
Level activated. Transition activated.
8.4.1 INTERRUPT ENABLE (IE) REGISTER
Table 22
Interrupt enable register bits
Table 23
Description of register bits
Philips Semiconductors Product specification
Low power single card reader TDA8029
Notes
Details on interaction with the UART behaviour in Power-down mode are described in Section 8.15. Do not write logic1sto reserved bits. These bits maybe usedin future 80C51 family productsto invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.4.2 INTERRUPT PRIORITY (IP) REGISTER
Table 24
Interrupt priority register bits
Table 25
Description of register bits
Note
Do not write logic1sto reserved bits. These bits maybe usedin future 80C51 family productsto invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.4.3 INTERRUPT PRIORITY HIGH (IPH) REGISTER
Table 26
Interrupt priority high register bits
Table 27
Description of register bits
Philips Semiconductors Product specification
Low power single card reader TDA8029
Note
Do not write logic1sto reserved bits. These bits maybe usedin future 80C51 family productsto invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.5 Dual Data Pointer (DPTR)

The dual DPTR structureisa wayby which the TDA8029
will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address
the external memory, anda singlebit called DPS (bit0of
the AUXR1 register) that allows the program code to
switch between them.
The DPSbit shouldbe savedby software when switching
between DPTR0 and DPTR1.
The GF bit (bit 2 in register AUXR1) is a general purpose
user-defined flag. Note that bit 2 is not writable and is
always read as a logic 0. This allows the DPS bit to be
quickly toggled simply by executing an INC AUXR1
instruction without affecting the GF or LPEP bits.
Theinstructions that referto DPTR referto the datapointer
thatis currently selected usingbit0of the AUXR1 register.
The six instructions that use the DPTR are listed in
Table 28 and an illustration is given in Fig.8.
Table 28
DPTR instructions
The data pointer canbe accessedona byte-by-byte basis
by specifying the low or high byte in an instruction which
accesses the SFRs.
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.6 Expanded data RAM addressing

The TDA8029 has internal data memory that is mapped
into four separate segments.
The four segments, shown in Fig.9, are: The lower 128 bytesof RAM (addresses 00hto 7Fh),
which are directly and indirectly addressable. The upper 128 bytesof RAM (addresses 80hto FFh),
which are indirectly addressable only. The Special Function Registers, SFRs, (addresses
80h to FFh), which are directly addressable only. The 512 bytes expanded RAM (XRAM 00h to 1FFh)
are indirectly accessedby move external instructions,
MOVX, if the EXTRAM bit (bit 1 of register AUXR) is
cleared.
The lower 128 bytes can be accessed by either direct or
indirect addressing. The upper 128 bytes canbe accessed
by indirect addressing only. The upper 128 bytes occupy
the same address space as the SFRs. That means they
have the same address, but are physically separate from
SFR space.
When an instruction accesses an internal location above
address 7Fh, the CPU knows whether the accessisto the
upper 128 bytes of data RAM or to the SFR space by the
addressing mode usedin the instruction. Instructions that
use direct addressing access SFR space. For example:
MOV A0h, #data accesses the SFR at location 0A0h
(which is register P2).
Instructions that use indirect addressing access the upper
128 bytes of data RAM. For example: MOV @R0, #data
where R0 contains 0A0h, accesses the data byte at
address 0A0h, rather than P2 (whose address is 0A0h).
The XRAM can be accessed by indirect addressing, with
EXTRAM bit (register AUXR bit 1) cleared and MOVX
instructions. This part of memory is physically located
on-chip, logically occupies the first 512 bytes of external
data memory.
When EXTRAM= 0, the XRAM is indirectly addressed,
using the MOVX instructionin combination with anyof the
registers R0,R1of the selected bankor DPTR.An access XRAM will not affect ports P0, P3.6 (WR) and P3.7 (RD).
P2 is output during external addressing. For example:
MOVX @R0, A where R0 contains 0A0h, access the
EXTRAM at address 0A0h rather than external memory.
An access to external data memory locations higher than
1FFh (i.e., 0200h to FFFFh) will be performed with the
MOVX DPTR instructions in the same way as in the
standard 80C51,so withP0 andP2as data/address bus,
and P3.6 and P3.7 as write and read timing signals.
When EXTRAM=1, MOVX @Ri and MOVX @DPTR will similarto the standard 80C51. MOVX @Ri will provide
an 8-bit address multiplexed with data on port 0 and any
output port pins can be used to output higher order
address bits. This is to provide the external paging
capability. MOVX @DPTR will generatea 16-bit address.
Port 2 outputs the high order eight address bits (the
contents of DPH) while port 0 multiplexes the low-order
eight address bits (DPL) with data. MOVX @Ri and
MOVX @DPTR will generate either read or write signals
on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the
256 bytes RAM (lower and upper RAM) internal data
memory. The stack must not be located in the XRAM.
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.6.1 AUXILIARY REGISTER (AUXR)
Table 29
Auxiliary register bits
Table 30
Description of register bits
Note
Do not write logic1sto reserved bits. These bits maybe usedin future 80C51 family productsto invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.7 Reduced EMI mode

When bit AO= 1 (bit 0 in the AUXR register), the ALE output is disabled.
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.8 Mask ROM devices

When none of the security bits SB1 and SB2 are
programmed, the code in the program memory can be
verified. If the encryption table is programmed, the code
willbe encrypted when verified. When only securitybit1is
programmed, MOVC instructions executed from external
program memory are disabled from fetching code bytes
from the internal memory. When security bitsSB1 andSB2
are programmed, in addition to the above, verify mode is
disabled.
The 64 bytes of the encryption array are initially not
programmed (all logic 1s).
Table 31
Program security bits for TDA8029
Note
Any other combination of the security bits is not
defined.
8.9 ROM code submission for 16 kbytes ROM
device TDA8029

When submitting ROM code for 16 kbytes ROM devices,
the following must be specified: 16 kbyte user ROM data 64 byte ROM encryption key ROM security bits.
8.10 Smart card reader control registers

The TDA8029 has one analog interface for five contacts
cards. The data to or from the card are fed into an ISO
UART.
TheCard Select Register (CSR) containsabitfor resetting
the ISO UART (logic0= active). This bit is reset after
power-on, and must be set to logic 1 before starting any
operation. It may be reset by software when necessary.
Dedicated registers allowto set the parametersof the ISO
UART: Programmable Divider Register (PDR) Guard Time Register (GTR) UART Control Registers (UCR1 and UCR2) Clock Configuration Register (CCR).
The parameters of the ETU counters are set by: Time-Out Configuration register (TOC) Time-Out Registers (TOR1, TOR2 and TOR3).
The Power Control Register (PCR)isa dedicated register
for controlling the power to the card.
When the specific parameters of the card have been
programmed, the UART may be used with the following
registers: UART Receive and Transmit Registers (URR and UTR) UART Status Register (USR) Mixed Status Register (MSR).
In reception mode, a FIFO of 1to 8 characters may be
used, and is configured with the FIFO Control Register
(FCR). This register is also used for the automatic
retransmission of NAKed characters in transmission
mode.
The Hardware Status Register (HSR) gives the status of
the supply voltage, the hardware protections, the SDWN
request and the card movements.
USR and HSR give interrupts on INT0_N when some of
their bits have been changed.
MSR does not give interrupts, and maybe usedin polling
mode for some operations. For this use, the bit TBE/RBF
within USR may be masked.
A 24-bit time-out counter may be started for giving an
interrupt after a number of ETU programmed in registers
TOR1, TOR2 and TOR3. It will help the controller for
processing different real time tasks (ATR, WWT, BWT,
etc.) mainlyif controllers and card clock are asynchronous.
This counteris configured with register TOC, that maybe
used as a 24-bit or as a 16-bit+ 8-bit counter. Each
counter maybe setfor startingto count once data written,
on detection of a start bit on I/O, or as auto-reload.
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.10.1 GENERAL REGISTERS
8.10.1.1 Card Select Register (CSR)
This register is used for resetting the ISO UART.
Table 32
Card select register, address 0h, read and write
Table 33
Description of register bits
8.10.1.2 Hardware Status Register (HSR)
This register gives the status of the chip after a hardware problem has been signalled or when pin SDWN_N has been
activated.
When PRTL1, PRL1, PTLor SDWNis logic1, then pin INT0_Nis LOW. The bits having caused the interrupt are cleared
when HSR is read (two fint cycles after the rising edge of signal RD).
In case of emergency deactivation by PRTL1, SUPL, PRL1 and PTL, bit START in the power control register is
automatically reset by hardware.
Table 34
Hardware Status Register, address Fh, read
Table 35
Description of register bits
Philips Semiconductors Product specification
Low power single card reader TDA8029
8.10.1.3 Time-Out Registers (TOR1, TOR2 and TOR3)
Table 36
Time-out register 1, address 9h, write
Table 37
Description of register bits
Table 38
Time-out register 2, address Ah, write
Table 39
Description of register bits
Table 40
Time-out register 3, address Bh, write
Table 41
Description of register bits
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