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TDA7705-TDA7705TR
Highly integrated tuner
September 2013 Doc ID 15938 Rev 9 1/42
TDA7705Highly integrated tuner for AM/FM car radio
Features Fully integrated VCO for world tuning High performance PLL for fast RDS system AM/FM mixers with high image rejection Integrated AM-LNA and AM-PINDIODE Automatic self alignment for preselection and
image rejection Digital IF signal processing, high performance
and drift-free Integrated IF-filters with high selectivity, high
dynamic range and adaptive bandwidth control RDS demodulation with group and block
synchronization High performance stereodecoder with
noiseblankerI2 C/SPI bus controlled Single 5 V supply LQFP64 package
DescriptionThe TDA7705 highly integrated tuner (HIT) is a
new generation of high performance tuners for
carradio applications.
It contains mixers and IF amplifiers for AM and
FM, fully integrated VCO and PLL synthesizer,
IF-processing including adaptive bandwidth
control, stereo decoder and RDS decoder on a
single chip.
The utilization of digital signal processing results
in numerous advantages against today's tuners:
very low number of external components, very
small space occupation and easy application,
very high selectivity due to digital filters, high
flexibility by software control and automatic
alignment.
Table 1. Device summary
Contents TDA77052/42 Doc ID 15938 Rev 9
Contents Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1 FM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 FM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 AM - LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 AM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 AM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 IF A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 Audio D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13.1 Serial interface choice / boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13.2 I2 C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13.3 SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.2 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.4 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.5 Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TDA7705 ContentsDoc ID 15938 Rev 9 3/42
3.4.6 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.7 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.8 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.9 I2 C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.10 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.11 Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.1 FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.2 AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.3 AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.4 AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.5 WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Front-end processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Weak signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.1 FM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.1 Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.3 Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.4 Stereo blend- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.5 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.6 Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 AM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.1 Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.3 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.1 Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Application schematic example with SPI-bus and tuned preselection . . . 39
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
List of tables TDA7705
4/42 Doc ID 15938 Rev 9
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Boot mode pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 15. I2 C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. AM LW overall system performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. WX overall system performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. Register 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23. Register 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24. Register 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. Register 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 26. Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27. Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 28. Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 29. Stereo blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 30. High cut control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 31. De-emphasis filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 32. Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 33. Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 34. Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 35. High cut control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TDA7705 List of figures
Doc ID 15938 Rev 9 5/42
List of figures
Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. I2 C "write" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. I2 C "read" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. SPI "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. SPI "read" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. I2 C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. SPI bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. FM input set-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. AM MW input set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. AM LW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. AM SW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. WX input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. FM wide-band application / I2 C control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. Example of FM tuned (narrow-band) application / SPI control . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. LQFP64 (10x10x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . . 40
Block diagram and pins description TDA7705 Doc ID 15938 Rev 9 Block diagram and pins description
1.1 Block diagram
Figure 1. Functional block diagram
TDA7705 Block diagram and pins description
Doc ID 15938 Rev 9 7/42
1.2 Pin description
Figure 2. Pin connection (top view)
Table 2. Pin description
Block diagram and pins description TDA7705
8/42 Doc ID 15938 Rev 9
Table 2. Pin description (continued)
TDA7705 Block diagram and pins description
Doc ID 15938 Rev 9 9/42
Table 2. Pin description (continued)
Function description TDA7705
10/42 Doc ID 15938 Rev 9
2 Function description
2.1 FM - mixers
The image-rejection mixer has two FM inputs, selectable through software. These inputs
feed stages with different gains, noise figures, and IIP3. They are optimized for best
performance in case of a passive tuned prestage and for a passive fixed bandpass without
tuning for low-cost application respectively.
The second input offers also the possibility of an easy addition of a weather-band
preselection filter.
The input frequency is downconverted to low IF with high image rejection.
The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is
performed automatically.
2.2 FM - AGC
The programmable RFAGC senses the mixer input whereas the IFAGC senses the IFADC
input to avoid overload.
The PIN diode driver is able to drive external PIN diodes with a current value as high as
15mA.
The time constant of the FM-AGC is defined by an external capacitor.
2.3 AM - LNA
The AM-LNA is integrated with low noise and high IIP2 and IIP3. The gain of the LNA is
controlled by the AGC. The maximum gain is set with an external resistor, typically 26 dB
with 1 k.
2.4 AM - AGC
The programmable AM-RF-AGC senses the mixer inputs and controls the internal PIN diode
and LNA gain.
First the LNA gain is reduced by about 10dB, then the PIN diodes are activated to attenuate
the signal.
The time constant of the AM-AGC is defined with an external capacitor and programmable
internal currents.
2.5 AM - mixers
The image-rejection mixer has two AM inputs selectable via software. It easily supports low-
cost applications for extended frequency bands like SW, DRM.
The input frequency is converted to low IF with high image rejection.
TDA7705 Function description
Doc ID 15938 Rev 9 11/42
2.6 IF A/D converters
A high performance IQ-IFADC converts the IF-signal to digital IF for subsequent digital
signal processing.
2.7 Audio D/A converters
A stereo DAC provides the left / right audio signals after IF-processing and stereodecoding
by the DSP.
2.8 VCO
The VCO is fully integrated without any external tuning component. It covers all FM
frequency bands including EU, US , Japan, EastEU, Weatherband and AM-bands including
LW, MW, SW.
2.9 PLL
The high speed tuning PLL is able to settle within about 300 µs for fast RDS applications.
The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.
2.10 Crystal oscillator
The device works with a 37.05 MHz fundamental tone crystal, and can be used also with a rd overtone 37.05 MHz crystal.
2.11 DSP
The DSP and its hardware accelerators perform all the digital signal processing. The main
program is fixed in ROM. Control parameters are copied in RAM and are accessible and
modifiable there, thus allowing parametric performance optimization.
It performs: digital down-conversion of IF bandwidth selection with variable controlled bandwidth FM and AM noiseblanking FM/AM demodulation with softmute, high-cut, weak signal processing and quality
detection FM stereo decoding with stereo blend RDS demodulation including error correction and block synchronization with generation
of an RDS interrupt for the main µP Autonomous control of RDS-AF tests Self alignment of preselection tuning
Function description TDA7705
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2.12 IO interface pins
The TDA7705 has the following IO pins:
The pins labeled GPIO0, 1, 2 and 3 (pins 43 to 40) are reserved.
The pin PLLTEST output voltage can be freely programmed via software and be used to
drive switches if needed by the application.
All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA
from the internal 3.3 V supply line.
2.13 Serial interface
The device is controlled with a standard I2 C bus or SPI interface.
Through the serial bus the processing parameters can be modifed and the signal quality
parameters and the RDS information can be read out.
The operation of the device is handled through high level commands sent by the main car-
radio µP through the serial interface, which allow to simplify the operations carried out in the
main µP . The high level commands include among others: set frequency (which allows to avoid computing the PLL divider factors); start seek (the seek operation can be carried out by the TDA7705 in a completely
autonomous fashion); RDS seek/search (jumps to AF and quality measurements are automatically
sequenced).
2.13.1 Serial interface choice / boot mode
The device can communicate with the main µP with two different standard serial protocols:
SPI and I2 C. The configuration is chosen by setting the proper value (0V or 3.3V) at pins 35
and 39 and it is latched (e.g. made effective) when the RSTN line transitions from low to
high (when RSTN is low, the IC is in reset mode).
The voltage level forced to pins 35 and 39 must be released to start the system operation a
suitable time after the RSTN line has gone high.
The list of configurations is shown in the following table:
PLLTEST pin 2 general purpose output
SPI_CS pin 34 serial communication with µP
SPI_MISO pin 35 serial communication with µP
SDA/MOSI pin 36 serial communication with µP
SCL/CLK pin 37 serial communication with µP
RDSINT pin 39 serial communication with µP
RSTN pin 45 reset pin driven by µP
TDA7705 Function description
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If I2 C serial bus is chosen as means of communication with the controlling device, two chip
addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins
35 and 39.
The status of pins 35 and 39 during the reset phase can be set to:
high, through external <10 k resistors tied to 3.3V (pin 32), or
low, by not forcing any voltage on them from outside, as 50 kohm internal pull-down
resistors are present on said pins. o make sure the boot mode is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and then for an
additional time Treset (see Section 3.4.8).
2.13.2 I2 C bus protocol2 C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires
an acknowledge after any 8-bit transmission.
A "write" communication example is shown in the figure below, for an unspecified number of
data bytes (see the relevant technical documentation for frame structure description):
Figure 3. I2 C "write" sequence
Table 3. Boot mode pin configuration
Function description TDA7705
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The sequence consists of the following phases: START: SDA line transitioning from H to L with SCL fixed H. This signifies a new
transmission is starting; data latching: on the rising SCL edge. The SDA line can transition only when SCL is
low (otherwise its transitions are interpreted as either a START or a STOP transition); ACKnowledge: on the 9th SCL pulse the µP keeps the SDA line H, and the TDA7705
pulls it down if communication has been successful. Lack of the acknowledge pulse
generation from the TDA7705 means that the communication has failed; a chip address byte must be sent at the beginning of the transmission. The value can
be C2 or C8 (according to the mode chosen at start-up during boot) for "write"; as many data bytes as needed can follow the address before the communication is
terminated. See the next section for details on the frame format; STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the
transmission.
Red lines represent transmissions from the TDA7705 to the µP.
A "read" communication example is shown in the figure below, for an unspecified number of
data bytes (see later on for frame structure decription):
Figure 4. I2 C "read" sequence
The sequence is very similar to the "write" one and has the same constraints for start, stop,
data latching. The differences follow: a chip address must always be sent by the µP to the TDA7705; the address must be C3
(if C2 had been selected at boot) or C9 (if C8 had been selected at boot); a header is transmitted after the chip address (the same happens for "write") before
data are transferred from the TDA7705 to the µP . See the relevant technical
documentation for details on the frame format; when data are transmitted from the TDA7705 to the µP , the µP keeps the SDA line H; the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the
TDA7705 to the µP. Failure of the µP to generate an ACK pulse on the 9th CLK pulse
has the same effect on the TDA7705 as a STOP.
The max. clock speed is 500 kbit/s.
2.13.3 SPI bus protocol
SPI requires four signals: clock (CLK), master output/slave input (MOSI - for communication
from the µP to the TDA7705), master input/slave output (MISO - for communication from the
TDA7705 to the µP), chip select (CS). CLK is generated by the master device and is used
for synchronization. MOSI and MISO are the data lines. The CS line is unique for each
device in an SPI bus. The µP pulls low the TDA7705 CS line to select it for communication.
The protocol does not foresee any transmission acknowledgement.
The SPI protocol has four possible modes of operation as far as data latching is concerned:
TDA7705 Function description
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Figure 5. SPI modes
In the case of the TDA7705, the data are latched on the clock's rising edge, with CPOL = 1
and CPHA = 1 (mode 3 in the figure above). According to the specification of this mode, the
polarity of the CLK line when no communication is taking place is high.
A "write" communication example is shown in the figure below, for an unspecified number of
bits (see the relevant technical documentation for frame structure description):
Figure 6. SPI "write" sequence
The start condition is signaled by the CS line going low, and the stop condition by the CS
line going high. It is not allowed to toggle the CS line while the communication is going on.
A "read" communication example is shown in the figure below, for an unspecified number of
bits (see the relevant technical documentation for frame structure description ):
Figure 7. SPI "read" sequence
The red line is controlled by the TDA7705, whereas the black lines are controlled by the µP.
Electrical specifications TDA7705
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3 Electrical specifications
3.1 Absolute maximum ratings
3.2 Thermal data
3.3 General key parameters
Table 4. Absolute maximum ratings
Table 5. Thermal data
Table 6. General key parameters In the typical application supplied from 5V with a series resistor. When the 1.2 V supply is applied externally, and not using the internal 1.2 V regulator.
TDA7705 Electrical specifications
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3.4 Electrical characteristics
VCC = 4.7 V to 5.25 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
3.4.1 FM - section
Table 7. FM - section The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature
dependency described by: I/Io = T/To, with Io being the current at ambient temperature (25 °C) and To the ambient
temperature (25°C) expressed in Kelvin, that is 298 K.
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3.4.2 AM - section
Table 8. AM - section The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature
dependency described by: I/Io = T/To, with Io being the current at ambient temperature (25 °C) and To the ambient
temperature (25 °C) expressed in Kelvin, that is 298 K.
TDA7705 Electrical specifications
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3.4.3 VCO
3.4.4 Phase locked loop
3.4.5 Tuning DAC
3.4.6 IF ADC
Table 9. VCO
Table 10. Phase locked loop
Table 11. Tuning DAC
Table 12. IF ADC
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3.4.7 Audio DAC
3.4.8 IO interface pins
Table 13. Audio DAC
Table 14. IO interface pins
TDA7705 Electrical specifications
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3.4.9 I2 C interface
The following parameters apply to the serial bus communication when I2 C protocol has
been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8
applies. The parameters of the following table are defined as in Figure8.
Figure 8. I2 C bus timing diagram
Table 15. I2 C interface
