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TDA7590STN/a1240avaiDigital signal processing IC for speech and audio applications


TDA7590 ,Digital signal processing IC for speech and audio applicationsElectrical characteristics for I/O pins . . . . 165 24 bit DSP core . . . . 176 Memories ..
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TDA7590
Digital signal processing IC for speech and audio applications
September 2013 Rev 3 1/42TDA7590
Digital signal processing IC for speech and
audio applications
Features
24-bit, fixed point, 120 MIPS DSP core Large on-board memory (128KW-24 bit) Host access to internal RAM through
expansion port Access to external RAM (16Mw) through
expansion port Integrated stereo, 18-bit Sigma-DELTA A/D
and 20-bit D/A converters Programmable CODEC sample rate up to kHz On-board PLL for core clock and converters External Flash/SRAM memory bank
management2 C and SCI serial interface for external control 2 enhanced synchronous serial interface
(ESSI)
•JTAG interface Host interface 144-pin TQFP, 0.50 mm pitch Automotive temperature range
(from -40 °C to +85 °C)
Applications
Real time digital speech and audio processing: speech recognition speech synthesis speech compression echo canceling noise canceling MP3 decoding
Description

The TDA7590 is a high performances, fully
programmable 24-bit, 120 MIPS. Digital signal
processor (DSP), designed to support several
speech and audio applications, as automatic
speech recognition, speech synthesis, MP3
decoding, echo and noise cancellation.
Nevertheless, the embedded CODECs bandwidth
and the generic processing engine allow to
proceed also full-band audio signals. The large
amount of on-chip memory (128 Kwords),
together with the 16 Mwords external memory
addressable and the 32 general purpose I/O pins
permit to build a DSP-system avoiding the usage
of an additional microcontroller.
The presence of serial and parallel interfaces
allows easy connection with external devices
including CODECs, DSPs, microprocessors and
personal computers.
In particular, the debug/JTAG interface permits
the on-chip emulation of the firmware developed.
Further, the presence of the timers and watchdog
block makes TDA7590 suitable for PWM
processing and allows the integration of a system
watchdog.

Table 1. Device summary
In ECOPACK® package (see Section 8: Package information on page 22).
Contents TDA7590
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Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 CODEC (ADC/DAC) test description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Electrical characteristics for I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Serial communication interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 I2 C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4 Host interface (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5 ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6 EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 Timers and watchdog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.8 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.9 CODEC cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TDA7590 Contents
3/42
9.1 Benchmarking program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
List of tables TDA7590
4/42
List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. General interface electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TDA7590 List of figures
5/42
List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block diagram TDA7590
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1 Block diagram
Figure 1. Block diagram
TDA7590 Pin description
7/42
2 Pin description
2.1 Pin connection
Figure 2. Pin connection (top view)
Pin description TDA7590
8/42
2.2 Pin function

Table 2. Pin function
TDA7590 Pin description
9/42
Table 2. Pin function (continued)
Pin description TDA7590
10/42
Table 2. Pin function (continued)
TDA7590 Pin description
11/42
Table 2. Pin function (continued)
Pin description TDA7590
12/42
Table 2. Pin function (continued)
TDA7590 Pin description
13/42
2.3 Thermal data


Table 2. Pin function (continued)
Table 3. Thermal data
Key parameters TDA7590
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3 Key parameters
3.1 Power consumption

Power consumption depends on application running and DSP clock frequency.
Supply current values are measured and guaranteed at testing level by adopting the
benchmarking program reported in Appendix 1.
Table 4. Key parameters
TDA7590 Key parameters
15/42
3.1.1 CODEC (ADC/DAC) test description

Reported typical values (table 3. - ADC and DAC sections) have been measured at Lab
level during product evaluation phase. General definitions and procedures are separately
defined in following dedicated paragraphs.
Total harmonic distortion with noise to signal (THD+N)/S

THD+N is defined as the ratio of the total power of the second power and higher harmonic
with noise components to the power of the fundamental for that signal. For THD+N
measurement, choose the DSP analyzer in digital analyzer with THD ratio as measurement
option. Measure the THD+N value at -3 dB amplitude of the input signal. First measure the
THD+N value at 1Vrms which is 0 dB reference and then measure the value at -3 dB
reference.
Dynamic range (DR)

DR is defined as the level of THD+N measured when the input sine wave amplitude is so
small that no harmonics apart from the fundamental tone are present in the output signal.
This way THD+N becomes practically the ratio between the whole signal and noise floor,
being a different way to express SNR. As a convention, at which no harmonics should be
present in the output signal, it is fixed at -40dB of the full scale amplitude.
Crosstalk or interchannel isolation

A disturbance, caused by electromagnetic interference, along a circuit or a cable pair. An
electric signal disrupts another signal in an adjacent circuit and can cause it to become
confused and cross over each other. Crosstalk is measured by applying a signal -3dB
amplitude of input signal at one channel (A) and no signal at an other channel (B),
measuring the effect on this channel (B) because of the channel (A).
Total harmonic distortion to signal (THD)/S

THD is defined as the ratio of the sum of only those components of the output signal which
are harmonic of system input, after having removed the fundamental tone corresponding to
the pure sine wave as input and the input signal.This measurement is done by using the
Harmonic analyzer which can isolate up to 15th harmonic components on the acquired
signal and report the sum of all of them, centering the fundamental tone on the frequency
provided by the input signal generator. These measurements are performed at -3dB
reference amplitude of input signal.
Table 4. Key parameters (continued)
Electrical specification TDA7590
16/42
4 Electrical specification
4.1 Absolute maximum ratings


4.2 Electrical characteristics for I/O pins



Table 5. Absolute maximum ratings
Table 6. Recommended DC operating conditions
All the specification are valid only within these recommended operating conditions.
Table 7. General interface electrical characteristics
TTL specifications only apply to the supply voltage range Vdd = 3.15V to 3.6V. Takes into account 200mV voltage drop in both supply lines. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
TDA7590 24 bit DSP core
17/42 24 bit DSP core
The DSP core is a general purpose 24-bit DSP . The main feature of the DSP core are listed
below: 120 MHz operating frequency (120 MIPS) Fully pipelined 24 x 24 bit parallel multiplier-accumulator Saturation/limiting logic 56-bit parallel barrel shifter Linear, reverse carry and modulo addressing modes 24-bit address buses for program, X and Y data spaces and DMA Memory-expandible hardware stack Nested zero-overhead DO loops Fast interrupts Powerful JTAG emulation port Software wait and stop low power standby modes Program address tracing support Two 24-bit data moves in parallel with arithmetic operations External interrupts including non-maskable interrupt Interrupts may be independently masked and prioritized Bit-manipulation instructions can access any register or memory location On board support for DMA controller
Memories TDA7590
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6 Memories

128 K x 24-bit RAM divided into 4 areas, program RAM(PRAM), X data RAM(XRAM), Y
data RAM(YRAM) and flexible allocation RAM(FLEX) as follows: 16 kB PRAM 40 kB FLEX RAM. FLEX RAM is accessed through the expansion port by the DSP
core. External access to the FLEX RAM is also supported. 72 kB RAM is allocated as XRAM and YRAM. Four configurations are supported: 4 kB XRAM and 68 kB YRAM 8 kB XRAM and 64 kB YRAM 16 kB XRAM and 56 kB YRAM 24 kB XRAM and 48 kB YRAM
TDA7590 DSP peripherals
19/42
7 DSP peripherals
7.1 Serial audio interface (SAI)

The SAI is used to communicate between the CODEC and the DSPs.
In addition, digital audio can be directly input for processing. There is only one SAI found on
the chip that can be accessed by either the DSP or the DMA controller. The main features of
this block are listed below: Slave operating modes, all clock lines can be inputs or outputs Transmit and receive interrupt logic triggers on left/right data pairs Receive and transmit data registers have two locations to hold left and right data
7.2 Serial communication interface (SCI)

The serial communication interface provides a full duplex port for serial communication to
other DSPs, microprocessors, and peripherals like modems.
The interface supports the following features: No additional logic for connection to other TTL level peripherals Asynchronous bit rates and protocols "High speed“ synchronous data
transmission. Asynchronous protocol includes Multidrop mode for master/slave operation with
wake-up on Idle line and wake-up on address bit capability, permitting the SCI to
share a single line with multiple peripherals Transmit and receive logic can operate asynchronously from each other. A programmable baud-rate generator which provide the transmit and receive
clocks or functions as a general purpose timer.
7.3 I2 C interface

The inter integrated-circuit bus is a simple bi-directional two-wire bus used for efficient inter
IC control. All I2 C bus compatible devices incorporate an on-chip interface which allows
them to communicate directly with each other via the I2 C bus.
Every component connected to the I2 C bus has it s own unique address whether it is a CPU,
memory or some other complex function chip. Each of these chips can act as a receiver
and/or transmitter depending on it s functionality.
7.4 Host interface (HI)

The host interface is a system-on-chip module that permits connection to the data bus of a
host processor. The HI is capable of driving 16 programmable external pins which can be
configured as an 8 bit parallel port for direct connection to a host processor.
DSP peripherals TDA7590
20/42
The key features of the host interface are: 8 bit parallel port "Full-duplex" dedicated host register bank Dedicated Mozart™ core DSP register core bank. Register banks map directly into Mozart X memory space 3 transfer modes: host command Host to Mozart core DSP Mozart core DSP to host Access protocols: Software polled Interrupt DMA access by the Mozart core DSP core 2+ wait states clock cycles per transfer Supported instructions: Data transfer between Mozart core and external host using Mozart MOVE
instruction Simple I/O service routine with bit addressing instructions IO service using fast interrupts with MOVEP instructions.
7.5 ESSI

The ESSI peripheral enables serial-port communication between the DSP core and external
devices including Codecs, DSP, microprocessors. The ESSI is capable of driving 12
programmable external pins which can be configured as GPIO ports C and D or ESSI pins.
The key features of the ESSI are: Independent receiver and transmitter Synchronous or asynchronous channel modes synchronous. Receiver and transmitter
use same clock/sync asynchronous. Receiver and transmitter may use separate
clock/sync up to one transmitter enabled in asynchronous channel mode. Up to three transmitters enabled in synchronous channel mode. Normal mode. One word per period. Network mode. Up to 32 words per period.
7.6 EOC

The Salieri extended on-chip memory interface provides access to 40 kB of on-chip
memory. The Mozart core will treat this memory as if it were external. Access by off-chip
expansion bus masters is permitted. All accesses to the extended on-chip RAM are
controlled by the extended on-chip memory control register. This register determines which
combinations of the Address attribute pins should be interpreted as accesses to the 40 kB of
RAM.
TDA7590 DSP peripherals
21/42
7.7 Timers and watchdog block

The timers and watchdog block consists of a common 21-bit prescaler and three
independent and identical general-purpose 24-bit timer/event counters, each with its own
register set.
Each timer has the following capabilities: Uses internal or external clocking. Interrupts the Mozart after a specified number of events (clocks). Signals an external device after counting internal events. Triggers DMA transfers after a specified number of events (clocks) occurs. Connects to the external world through designated pins TIO[0-2] for timers 0-2.
When TIO is configured as an Input: timer functions as an external event counter. Timer measures external pulse
width/signal period. Output: timer functions as a:
–Timer Watchdog timer Pulse-width modulator.
7.8 PLL

The PLL generates the following clocks: DCLK: DSP core clock DACLK: ADC and DAC clock LRCLK: left/right clock for the SAI and the CODEC SCLK: shift serial clock for the SAI and the CODEC
7.9 CODEC cell

The main features of the CODEC cell are listed below: 20 bits stereo DAC, and 18 bits ADC 2 S format Oversampling ratio: 512 Sampling rates of 8 kHz to 48 kHz
The analog interface is in the form of differential signals for each channel. The interface on
the digital side has the form of an SAI interface and can interface directly to an SAI channel
and then to the DSP core.
DCLK can be supplied either by the internal PLL or by external, to allow synchronization
with external anal digital sources.
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