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TDA7479STN/a2118avaiSINGLE CHIP RDS DEMODULATOR + FILTER
TDA7479ADTRSTN/a3009avaiSINGLE CHIP RDS DEMODULATOR + FILTER
TDA7479DTRSTN/a3196avaiSINGLE CHIP RDS DEMODULATOR + FILTER


TDA7479DTR ,SINGLE CHIP RDS DEMODULATOR + FILTERTDA7479SINGLE CHIP RDS DEMODULATOR + FILTER1
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TDA7479-TDA7479ADTR-TDA7479DTR
SINGLE CHIP RDS DEMODULATOR + FILTER
1/8
TDA7479

December 2004 FEATURES VERY HIGH RDS DEMODULATION QUALITY
WITH IMPROVED DIGITAL SIGNAL
PROCESSING HIGH PERFORMANCE, 57KHz BANDPASS
FILTER (8th ORDER) FILTER ADJUSTMENT FREE AND WITHOUT
EXTERNAL COMPONENTS PURELY DIGITAL RDS DEMODULATION
WITHOUT EXTERNAL COMPONENTS ARI (SK INDICATION) AND RDS SIGNAL
QUALITY OUTPUT 4.332MHz CRYSTAL OSCILLATOR(8.664 and
17.328MHz OPTIONAL) LOW NOISE CMOS TECHNOLOGY LOW RADIATION DESCRIPTION
The TDA7479 recovers the additional inaudible RDS
information which is transmitted by FM radio broad-
casting stations and operates in accordance with the
EBU (European Broadcasting Union) specifications.
The device is made up of two sections: a cascaded
antialiasing + switched capacitors 8th bandpass filter
for precise RDS band selection and a demodulating
section that performs the extraction od RDS data
stream (RDDA) and clock (RDCL), to be further pro-
cessed by a suitable RDS decoder.
Outputs for RDS signal quality and ARI indication are
also present.
SINGLE CHIP RDS DEMODULATOR + FILTER
Figure 2. Block Diagram

Rev. 6
TDA7479
Table 2. Pin Description
Figure 3. Pin Connection (Top view)
Table 3. Thermal Data
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TDA7479
Table 4. Absolute Maximum Ratings

(1) The 3rd harmonic (57kHz) must be less than -40dB with respect to the input signal plus gain.
Table 5. Electrical Characteristcs

(Tamb = 25°C, VS = 5V, unless otherwise specified)
TDA7479
Figure 4. RDS timing diagram OUTPUT TIMING

The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data. According to the internal
PLL lock condition data change can result on the falling or on the rising clock edge. (see Fig. 4)Whichever clock
edge is used by the decoder (rising or falling edge) the data will remain valid for 416.7 µs after the clock transi-
tion. OSCILLATOR CONTROLS (FSEL, OSEL)
Three different crystal frequencies can be used. The adaption of the internal clock divider to the external crystal
is achieved via the input pin FSEL. See the following table for reference:
Table 6.

A special mode is introduced to reduce EMI. With pin OSEL connected to GND the internal oscillator is switched
off and an external sinusoidal frequency could be applied on OSCIN. The peak to peak voltage of this signal
can be reduced down to 60mV.
In this mode the frequency selection via FSEL is still active.
Suggested values of C1 and C2 are shown in the following table:
Table 7.
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TDA7479
Figure 5. SO16 Mechanical Data & Package Dimensions
TDA7479
Figure 6. TSSOP16 Mechanical Data & Package Dimensions
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