IC Phoenix
 
Home ›  TT25 > TDA7467D013TR,AUDIO MATRIX WITH SRS EFFECTS
TDA7467D013TR Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
TDA7467D013TRSTN/a894avaiAUDIO MATRIX WITH SRS EFFECTS


TDA7467D013TR ,AUDIO MATRIX WITH SRS EFFECTSTDA7467AUDIO MATRIX WITH SRS EFFECTSThe Device incorporates the SRS(Sound Retrieval System) underli ..
TDA7468D ,TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUNDTDA7468D®TWO BANDS DIGITALLY CONTROLLEDAUDIO PROCESSOR WITH BASS ALC SURROUNDINPUT MULTIPLEXER- 4 S ..
TDA7468D13TR ,TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUNDapplications in Hi-Fi systems.– INDEPENDENT MUTE FUNCTIONSelectable input gain is provided. Control ..
TDA7468D13TR ,TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUNDELECTRICAL CHARACTERISTICS (refer to the test circuit T = 25°C, V = 9V, f = 1KHz all controls flat ..
TDA7468D13TR ,TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUNDBLOCK DIAGRAM2/22MUX-R IS-R TREBLE-R BASSI-R BASSO-R23 22 21 20 19 18IN-R450K50KgmINPUTbuffer gain: ..
TDA7469 ,LOW VOLTAGE ANALOG AUDIO PROCESSOR WITH HEADPHONE POWER AMPLIFIERFEATURES Figure 1. Package■ 2 STEREO INPUT■ 1 STEREO OUTPUT■ TREBLE BOOSTSSOP24■ BASS CONTROL■ BASS ..
THS3001ID ,420-MHz Current-Feedback AmplifierMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)THS3001 THS3001HV ..
THS3001IDGN ,420-MHz Current-Feedback AmplifierELECTRICAL CHARACTERISTICSAt T = 25°C, R = 150Ω , R = 1 kΩ (unless otherwise noted)A L F(1)PARAMETE ..
THS3001IDGNR ,420-MHz Current-Feedback Amplifier.(1)ABSOLUTE
THS3001IDR ,420-MHz Current-Feedback AmplifierDGN−8D−8 THS3001
THS3061D ,High-Voltage, High Slew-Rate Current Feedback Amplifiermaximum ratings under any condition is limited by the constraints of the silicon process. Stresses ..
THS3061DGN ,High-Voltage, High Slew-Rate Current Feedback Amplifier SLOS394B –JULY 2002–REVISED NOVEMBER 2009(1)ORDERING INFORMATIONPART NUMBER PACKAGE TYPE PACKAGE M ..


TDA7467D013TR
AUDIO MATRIX WITH SRS EFFECTS
1/11
TDA7467

November 2003 1 STEREO INPUT INPUT ATTENUATION CONTROL IN 0.5dB STEP MUTE FUNCTION MONO MODE (SRS 3D MONO) STEREO MODE (SRS 3D STEREO) SPACE AND CENTER ATTENUATORS ARE
AVAILABLE ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS (I2 C BUS)
DESCRIPTION

The TDA7467 is a SRS (Sound Retrieval System)
audio matrix. It reproduces SRS sound processing
stereo and mono sources both.
The SRS sound is guaranteed by external compo-
nents and it is not affected by internal process
spreads.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers according to the SRS labs specification.
Control of all the functions is accomplished by se-
rial bus. Thanks to the used BIPOLAR/CMOS/
DMOS technology, Low Distortion, Low Noise and
DC stepping are obtained.
AUDIO MATRIX WITH SRS EFFECTS
PIN CONNECTION (Top view)
TDA7467
2/11
BLOCK DIAGRAM
3/11
TDA7467
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
QUICK REFERENCE DATA
ELECTRICAL CHARACTERISTCS

Refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat
(G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified
SUPPLY
TDA7467
4/11
SRS SURROUND SOUND MATRIX
ELECTRICAL CHARACTERISTCS (continued)

Refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat
(G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified
5/11
TDA74672 C BUS INTERFACE

Data transmission from microprocessor to the TDA7467 and vice versa takes place through the 2 wires2 C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
Data Validity

As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions

As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
Acknowledge

The master (μP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio processor, the μP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 1. Data Validity on the I
2 CBUS
Figure 2. Timing Diagram of I
2 CBUS
Figure 3. Acknowledge on the I2 CBUS
TDA7467
6/11
SOFTWARE SPECIFICATION

Interface Protocol
The interface protocol comprises: A start condition (S) A chip address byte A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
ACK = Acknowledge
S = Start; P = Stop
A = Address
B = Auto Increment
EXAMPLES
No Incremental Bus

The TDA7467 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no
incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
Incremental Bus

The TDA7467 receive a start conditions, the correct chip address, a subaddress with the MSB = 1 (incre-
mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "1XXXX1XX" to "1XXX111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent
in the loop etc, and at the end it receivers the stop condition.
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED