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TDA7439DS13TRSTN/a4750avaiTHREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR


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TDA7439DS13TR
THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR
1/19
TDA7439DS

June 2004
1FEATURES
INPUT MULTIPLEXER 4 STEREO INPUTS SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
2DESCRIPTION

The TDA7439DS is a volume tone (bass, middle
and treble) balance (Left/Right) processor for
quality audio applications in car-radio and Hi-Fi
systems. Selectable input gain is provided. Con-
trol of all the functions is accomplished by serial
bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers. Thanks to the used BIPOLAR/CMOS
Technology, Low Distortion, Low Noise and DC
stepping are obtained
THREE BANDS
DIGITALLY CONTROLLED AUDIO PROCESSOR
Figure 2. Block Diagram

REV.2
TDA7439DS
Figure 3. PIN CONNECTION
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Table 4. QUICK REFERENCE DATA
3/19
TDA7439DS
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω,

all controls flat (G = 0dB), unless otherwise specified)
TDA7439DS
Notes:1. The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device. BASS, MIDDLE and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
Table 5. Electrical Characteristcs (continued)
5/19
TDA7439DS
Figure 4. TEST CIRCUIT APPLICATION SUGGESTIONS

The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free
from any noisy acoustical effect. The TDA7439DS audioprocessor provides 3 bands tones control.
3.1 Bass, Middle Stages

The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44KΩ
typical.
The Middle cell has an internal resistor Ri = 25KΩ typical.
Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT
pins.
Figure 5.
TDA7439DS
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
3.2 Treble Stage

The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground Typical responses are reported in Figg.
10 to 13.
3.3 CREF

The suggested 10µ F reference capacitor (CREF) value can be reduced to 4.7µ F if the application requires
faster power ON.
Figure 6. THD vs. frequency Figure 7. THD vs. RLOAD
7/19
TDA7439DS
Figure 8. Channel separation vs. frequency
Figure 9. Bass response
Figure 10. Treble response
Figure 11. Middle response
Figure 12. Typical tone response
TDA7439DS 2 C BUS INTERFACE
Data transmission from microprocessor to the TDA7439DS and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity

As shown in fig. 13, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions

As shown in fig.14 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge

The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
15). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler transmission:
simply it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 13. Data Validity on the I
2 CBUS
Figure 14.
9/19
TDA7439DS
Figure 15. SOFTWARE SPECIFICATION
5.1 Interface Protocol

The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7439DS address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
Figure 16.

ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment EXAMPLES
6.1 No Incremental Bus

The TDA7439 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incre-
mental bus), N-data (all these data concern the subaddress selected), a stop condition.
Figure 17.
TDA7439DS
6.2 Incremental Bus

The TDA7439DS receive a start conditions, the correct chip address, a subaddress with the B = 1 incre-
mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the
loop etc, and at the end it receivers the stop condition.
Figure 18.
Table 6. POWER ON RESET CONDITION DATA BYTES

Address = 88 HEX (ADDR:OPEN).
Figure 19. FUNCTION SELECTION: First byte (subaddress)

B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
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