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TDA7421NSTN/a4320avaiAM/FM TUNER FOR CAR RADIO AND HI-FI APPLICATIONS


TDA7421N ,AM/FM TUNER FOR CAR RADIO AND HI-FI APPLICATIONSAPPLICATIONS■ AM DOUBLE CONVERSION ARCHITECTURETQFP64■ AM/FM STATION DETECTOR AND DIGITAL ORDERING ..
TDA7427AD ,AM-FM RADIO FREQUENCY SINTHESIZER AND IF COUNTERELECTRICAL CHARACTERISTICS (Tamb = 25°C; VDD1 = 5V; VDD2 = 10V; fOSC = 4MHz; unless other-wise spec ..
TDA7427AD1 ,AM-FM RADIO FREQUENCY SINTHESIZER AND IF COUNTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage - 0.3 to + 7 VDD1V Supply Volta ..
TDA7427D ,AM-FM RADIO FREQUENCY SYNTHESIZER AND IF COUNTERTDA7427®AM-FM RADIO FREQUENCY SYNTHESIZERAND IF COUNTERON-CHIP REFERENCE OSCILLATOR ANDPROGRAMMABLE ..
TDA7429L ,3 BAND EQUALIZER AUDIO PROCESSOR WITH SUBWOOFER CONTROLapplications in TV and Hi-Fi systems, providing alsoFigure 1. Test Circuit2.2m F 2.2m F0.47m F 0.47 ..
TDA7429S ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXapplications in TV and Hi-Fi systems. obtained.PIN CONNECTION (TQFP44)44 43 42 41 40 39 38 37 36 35 ..
THS0842 ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownblock diagramAVDDDRV DVDD DDCOUTCLK Timing CircuitryCOUTI +Sample& HoldI –DA(7–0)3-State8 BITBUSMUX ..
THS0842IPFB ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownTHS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTERWITH SINGLE OR DUAL PARALLE ..
THS10064 ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerFEATURES DESCRIPTION* High-Speed 6 MSPS ADCThe THS10064 is a CMOS, low-power, 10-bit, 6 MSPS* 4 Ana ..
THS10064CDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTHS10064DGND to D ..
THS10064CDAR ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerELECTRICAL CHARACTERISTICS over recommended operating conditions, AV = 5 V, DV = BV = 3.3 V, f = ..
THS10064IDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Powermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..


TDA7421N
AM/FM TUNER FOR CAR RADIO AND HI-FI APPLICATIONS
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TDA7421N

August 2000 HIGH PERFORMANCE FRONT-END IC FOR
AM/FM RECEIVERS FULLY INTEGRATED HIGH-SPEED PLL FOR
OPTIMIZED RDS APPLICATIONS FM MPX/AM AUDIO OUTPUT, 450kHz AM IF
OUTPUT FOR STEREO AM APPLICATIONS AM DOUBLE CONVERSION ARCHITECTURE AM/FM STATION DETECTOR AND DIGITAL
IF-COUNTER SINGLE FREQUENCY REFERENCE FOR
BOTH AM AND FM FULL ELECTRICAL ADJUSTMENTI2 C-BUS PROGRAMMABLE
DESCRIPTION

The TDA7421N is a high-performance tuner circuit
which integrates AM and FM sections, PLL frequency
sinthesizer and IF counter on a single chip.
Use of BICMOS technology allows the implementa-
tion of tuning functions with a minimum of external
components.Value spread of external components
can be fully compensated by means of on-chip elec-
trical adjustment controlled by external μP.
The FM quality detection circuit, in conjunction with
the digital IF counter, enables the stop-station func-
tion in “seek” mode and MPX mute during reception.
The combination of programmable level detector and
IF counter allows reliable AM stop-station perfor-
mance.
The Automatic Gain Control (AGC) operates on dif-
ferent signal bandwidths in order to optimize sensitiv-
ity and dynamic range.2 C-bus controls functions such as AGC, amplifier
gains, PLL and counter settings.
PRELIMINARY DATA

AM/FM TUNER FOR CAR RADIO AND HI-FI APPLICATIONS
PIN CONNECTIONS
TDA7421N
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BLOCK DIAGRAM
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TDA7421N
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN DESCRIPTION
TDA7421N
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PIN DESCRIPTION (Continued)
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TDA7421N

(*) Pin function is user defined by software.
PIN DESCRIPTION (Continued)
TDA7421N
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FM SECTION GLOBAL PERFORMANCES

Refer to Evaluation Circuit
– Input 98.1MHz, 40KHz dev., 1KHz mod., 60dBμV antenna level, mono.
– MPX Output, de-enphasis 50μs, BPF 200Hz-15KHz.
AM SECTION GLOBAL PERFORMANCES

Refer to Evaluation Circuit
- Input: fc = 999KHz, f mod = 400Hz, m = 30%, 74dBμVemf antenna level unless otherwise specified.
- Audio Output + RC BPF (BPF 20Hz - 20KHz)
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TDA7421N
ELECTRICAL CHARACTERISTICS
DC PARAMETERS (Tamb = 25°C; VCC = 8V, Vdd = 5V, no RF input unless otherwise specified)
Voltage Controlled Oscillator (VCO)

Ref: FM Test Circuit, measure Vosc with high impedance FET probe
TDA7421N
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Reference Oscillator

Ref: AM Test Circuit, measureVXTAL with high impedance FET probe
FM Front-end Electrical Adjustments

Ref: FM Test Circuit, measure VANTADJ and VRFADJ referred to VPLLOUT
FM Mixer

Ref: FM Test Circuit, measure input at VMIXFMIN, output at VMIXOUT
FM AGC

Ref: FM Test Circuit, measure input at VFMRFAGCIN and VFMIFAGCIN, output at VFMAGCOUT
ELECTRICAL CHARACTERISTICS (Continued)
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TDA7421N
FM IF Amplifier 1

Ref: FM Test Circuit, measure input at VFMAMP1IN, output at VFMAMP1OUT
FM IF Amplifier 2

Ref: FM Test Circuit, measure input at VFMAMP2IN, output at VFMAMP2OUT
FM Limiter, Field Strengh Meter and Demodulator

Ref: FM Test circuit, measure:
- Input at VFMLIMIN, fIN = 10.7MHz
- FS Meter output at VFMSMETER (FMADJ set to 0, FSL4-0 set to 00000)
- demodulator adjustment output at VFSMETER (FMADJ set to 1)
ELECTRICAL CHARACTERISTICS (Continued)
TDA7421N
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FM Audio Amplifier

Ref: FM Test circuit, VFMLIMIN, = 95dBμV, fIN = 10.7MHz; measure:
- MPX output at VAUDIO, BPF 200Hz to 15KHz, 50μs de-emphasis.
- muting voltage at VMUTE, DRIVE
FM QUALITY DETECTORS
Field Strength Detector

Ref: FM Test Circuit, HDDIS and BWDIS set to 1, measure:
- Input at VFMLIMIN, fIN = 10.7MHz, CW
- output at VMUTE,DRIVE
ELECTRICAL CHARACTERISTICS (Continued)
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TDA7421N
Detuning Detector

Ref: FM Test Circuit; HDDIS and SMDIS set to 1, measure:
- Input at VFMLIMIN, CW
- output at VMUTE,DRIVE
Adjacent Channel Detector

Ref: FM Test Circuit; BWDIS and SMDIS set to 1, measure:
- Input at VFMLIMIN: desired 10.7MHz, 95dBμV CW; undesired 10.8MHz CW
- output at VMUTE,DRIVE
Field Strength Station Detector

Ref: FM Test Circuit; SEEK set to 1, HDDIS and BWDIS set to 1, measure:
- Input at VFMLIMIN: desired 10.7MHz, CW
- output at VFMSD
ELECTRICAL CHARACTERISTICS (Continued)
TDA7421N
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Detuning Station Detector

Ref: FM Test Circuit; SEEK set to 1, HDDIS and SMDIS set to 1, measure:
- Input at VFMLIMIN, CW;
- output at VFMSD
Adjacent Channel Station Detector

Ref: FM Test Circuit; SEEK set to 1, HDDIS and SMDIS set to 1, measure:
- Input at VFMLIMIN: desired 10.7MHz, 95dBμV CW; undesired 10.8MHz CW
- output at VFMSD
AM Mixer 1

Ref: AM Test Circuit, measure input at VMIX1AMIN, output at VMIXOUT
AM Wide & Narrow AGC

Ref: AM Test Circuit; measure input at VMIX1AMIN and VMIX2AMIN, output at VAMAGC1AMP and VAMAGC1PIN
ELECTRICAL CHARACTERISTICS (Continued)
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TDA7421N
AM Mixer 2

Ref: AM Test Circuit; measure input at VMIX2AMIN, output at VMIX2OUT (switches must be in position 2 for AGC
measurements).
AM IF2 Amplifier

Ref: AM Test Circuit; fIN = 450KHz, measure input at VIF2AMPIN, output at VIF2AMPOUT (switches must be in position 1).
ELECTRICAL CHARACTERISTICS (Continued)
TDA7421N
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AM Field Strength Meter and Field Strength Station Detector

Ref: AM Test Circuit; fIN = 10.7MHz, measure input at VMIX2AMIN, outputs at VAMSMETER and at VAMSD (switches in
position 2).
IF Counter Output

Ref: AM & FM Test Circuit, measure at pin 28
SD output Impedance

Measure output at VFMSD
Loop Filter Input/Output

(LP_IN1, LP_IN2, LP_IN3, LP_OUT)
ELECTRICAL CHARACTERISTICS (Continued)
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TDA7421N2 C Bus Interface
ELECTRICAL CHARACTERISTICS (Continued)
TDA7421N
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Figure 1. AM Test Circuit
Figure 2. FM Test Circuit
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TDA7421N
1.0 FM SECTION

Featuring a single conversion configuration, it comprises a multi-stage IF limiter whose gain is I2 C controlled
and a quadrature demodulator with detuning and adjacent channel detectors. Signal meter and stop station
functions are also supported
2.0 AM SECTION

AM signal is converted by means of UP-DOWN configuration (IF1 = 10.7MHz, IF2 = 450KHz) and MW/LW
bands are covered.
3.0 PLL SECTION

Three operating modes are available:
They are user programmable with the mode PM registers.
3.1 Standby mode

It stops all functions. This allows low current consumption without loss of information in all registers. The pin LP-
OUT is forced to 0V in power on. All data registers are set to FE (11111110). The oscillator does not run in stand-
by mode.
3.2 FM and AM Operation

The FM or AM signal applies to a 32/33 prescaler, which is controlled by a 5 bit counter (A). The 5 bit register
(PC0 to PC4) controls this divider.
The output of the prescaler connects to a 11 bit divider (B). The 11 bit register (PC5 to PC15) controls the divider 'B'.
3.2.1 THREE STATE PHASE COMPARATOR

The phase comparator generates a phase error signal according to phase difference between fSYN and fREF.
This phase error signal drives the charge pump current generator.
3.2.2 CHARGE PUMP CURRENT GENERATOR

This stage generates signed pulses of current. The phase error signal decides the duration and polarity of those
pulses.The current absolute values are programmable by A0, A1, A2 registers for high current and B0, B1 reg-
isters for low current.
3.2.3 LOW NOISE CMOS OP-AMP

An internal voltage divider at pin VREF connects the positive input of the low noise Op-Amp.The charge pump
output connects the negative input. This internal amplifier in cooperation with external components can provide
an active filter. The negative input is switchable to three input pins (LPIN 1, LPIN 2 and LPIN 3), to increase the
flexibility in application.This feature allows two separate active filters for different applications.A logical "1" in the
LPIN 1/2 register activates pin LPIN 1, otherwise pin LPIN 2 is active. While the high current mode is activated
LPIN 3 is switched on.
TDA7421N
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3.2.4 INLOCK DETECTOR

The charge pump is switched in low current mode as the truth table and the related figure shows.
The charge pump is forced in low current mode when a phase difference of 10-40 usec is reached.
A phase difference larger than the programmed values will switch the charge pump immediately in the high cur-
rent mode.
Few programmable delays are available for inlock detection.
4.0 IF COUNTER SYSTEM FOR AM/FM

The IF counter mode is controlled by IFCM register:
A sample timer to generate the gate signal for the main counter is built with a 14 bit programmable counter to
have the possibility to use any frequency. In FM mode a 6.25 KHz, in AM mode a 1KHz signal is generated.
This counter is followed by an asynchronous divider to generate several sampling times.
ADDRESS ORGANIZATION (PLL and IF Counter)
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TDA7421N
4.1 Intermediate Frequency Main Counter (IFMC)

This counter is a 13-21 bit synchronous autoreload down-counter. Four bits are programmable to have the pos-
sibility for an adjust to the frequency of the IF filter.The counter length is automatically adjusted to the chosen
sampling time and the counter mode. At the start the counter will be loaded with a defined value which is an
equivalent to the divider value (tsample fIF).If a correct frequency is applied to the IF counter frequency inputs
IF-AM and IF-FM, at the end of the sampling time the main counter is changing its state from 0 to 1FFFFFH.This
is detected by a control logic. The frequency range inside which a successful count results is detected is adjust-
able setting bits EW 0, 1, 2.
4.2 Up-down counter filter

The information coming from the IF main counter control logic is shifted into a 5 bit up down counter circuit
clocked by the sampling time signal. At the start (rising edge of the IFENA signal) the counter is set to 10H and
the SSTOP signal is forced to "1".Only when the counter reaches the value 10H - step, SSTOP goes to "0".SS-
TOP will be "1" again, if the counter reaches the value 10h + step.
Figure 3. Charge Punp Logic
Figure 4. FM and AM operation (swallow mode)
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