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TDA7346D
DIGITAL CONTROLLED SURROUND SOUND MATRIX
TDA7346DIGITAL CONTROLLED SURROUND SOUND MATRIX
1 STEREO INPUT
THREE INDEPENDENT SURROUND MODES
ARE AVAILABLE MOVIE, MUSIC AND SIMU-
LATED
- MUSIC: 4 SELECTABLE RESPONSES
- MOVIE AND SIMULATED:
256 SELECTABLE RESPONSES
TWO INDEPENDENT INPUT ATTENUATORS
IN 0.31dB FOR BALANCE FACILITY
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
DESCRIPTIONThe TDA7346 reproduces surround sound by us-
ing phase shifters and a signal matrix. Control of
all the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
BLOCK DIAGRAM
THERMAL DATA
QUICK REFERENCE DATA
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTION
TDA73462/14
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,RG = 600Ω, all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
SUPPLY
INPUT STAGE
EFFECT CONTROL
TEST CIRCUIT
TDA7346
ELECTRICAL CHARACTERISTICS (continued)
SURROUND SOUND MATRIX
TDA73464/14
ELECTRICAL CHARACTERISTICS (continued)
AUDIO OUTPUTS
GENERAL
BUS INPUTSNote:
(1) Bass and Treble response: The center frequency and the resonance quality can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network.
(2) The peak voltage of the two input signals must be less then VS:
(Lin + Rin) peak • AVin < VS
TDA7346
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7346 and viceversa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data ValidityAs shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio-
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA73466/14
SOFTWARE SPECIFICATIONInterface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7346
address (the 8th bit of the byte must be 0). The
TDA7346 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N bytes + achnowledge).
A stop condition (P)
SOFTWARE SPECIFICATIONChip address
A = Logic level on pin ADDR
A = 1 if ADDR pin = open
A = 0 if ADDR pin = connected to ground
Software Specification
TDA7346
