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TDA7345DST ?N/a111avaiDIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
TDA7345DSTN/a700avaiDIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
TDA7345DN/a95avaiDIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX


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TDA7345D
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
TDA7345
DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH SURROUND SOUND MATRIX
1 STEREO INPUT
VOLUME CONTROL IN 1.25dB STEP
TREBLE AND BASS CONTROL
THREE SURROUND MODES ARE AVAIL-
ABLE:
– MOVIE, MUSIC AND SIMULATED
FOUR SPEAKER ATTENUATORS:
– 4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
DESCRIPTION

The TDA7345 is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in car radio and Hi-Fi systems.
It reproduces surround sound by using phase
shifters and a signal matrix. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
PIN CONNECTION
BLOCK DIAGRAM
TDA7345

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TEST CIRCUIT
THERMAL DATA
QUICK REFERENCE DATA
ABSOLUTE MAXIMUM RATINGS
TDA7345

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ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,
RG = 600Ω, all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
SUPPLY
INPUT STAGE
VOLUME CONTROL
BASS CONTROL (1)
TREBLE CONTROL (1)
EFFECT CONTROL
TDA7345

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ELECTRICAL CHARACTERISTICS (continued)
SURROUND SOUND MATRIX
TDA7345

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ELECTRICAL CHARACTERISTICS (continued)
SPEAKER ATTENUATORS (REC_OUT_L, REC_OUT_R)
SPEAKER ATTENUATORS (LOUT, ROUT)
AUDIO OUTPUTS (LOUT, ROUT, REC_OUT_L, REC_OUT_R)
GENERAL
BUS INPUTS
Note:
(1) Bass and Treble response: The center frequency and the resonance quality can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network.
(2) The peack voltage of the two input signals must be less then VS:
(Lin + Rin) peak • AVin < VS
TDA7345

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2 C BUS INTERFACEData transmission from microprocessor to the
TDA7345 and viceversa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 3: Data Validity on the I
2 CBUS
Figure 4: Timing Diagram of I
2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA7345

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INTERFACE FEATURES
- Due to the fact that the MSB is used to select
if the byte transmitted is a subaddress (func-
tion) or a data (value), between a start and
stop condition, is possible to receive, how
many subaddresses and datas as wanted.
- The subaddress (function) is fixed until a new
subaddress is transmitted, so the TDA7345
can receive how many data as wanted for the
selected subaddress (without the need for a
new start condition)
- If TDA7345 receives a subaddress with the
LSB = 1 the incremental bus is selected, so it
enters in a loop condition that means that
every acknowledge will increase automat-
ically the subaddress (function) and it re-
ceives the data related to the new subad-
dress.
EXAMPLES

1) NO INCREMENTAL BUS
TDA7345 receives a start condition, the correct
chip address, a subaddress with the LSB = 0 (no
incremental bus), N-datas (all these datas con-
cern the subaddress selected), a new subad-
dress, N-data, a stop condition.
So it can receive in a single transmission how
many subaddress are necessary, and for each
subaddress how many data are necessary.
2) INCREMENTAL BUS
TDA7345 receives a start condition, the correct
chip address a subaddress with the LSB = 1 (in-
cremental bus): now it is in a loop condition with
an autoincrease of the subaddress.
The first data that it receives doesn’t concern the
subaddress sended but the next one, the second
one concerns the subaddress sended plus two in
the loop etc, and at the end it receives the stop
condition.
In the pictures there are some examples:
S = start
ACK = acknowledge
B = 1 incremental bus, B = 0 no incremental bus
P = stop
SOFTWARE SPECIFICATION

the end of each transmitted byte.
A subaddress (function) bytes (identified by the
1) one subaddress, with n data concerning that subaddress (no incremental bus)
ACK = Achnowledge
S = Start
P = Stop
Data Transferred (N-bytes + Acknowledge)
TDA7345

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B = 1 yes incremental bus;
B = 0 no incremental bus;
X = indifferent 0,1
The first byte select the function, it is identified by the MSB = 0
DATA BYTES

FUNCTION SELECTION
FIRST BYTE (subaddress)
2) one subaddress, (with incremental bus) , with n data (data1 that concerns subaddress +1, data 2
that concerns subaddress + 2 etc.)
3) more subaddress with more data
TDA7345

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