TDA7333 ,RDS/RBDS PROCESSORBlock DiagramCxti CxtoCref Cref Cref16pF 16pFREF1 REF2 REF3 VDDA VSS VDDDXTI XTO4 3 2 9 10 1 5 7OSC ..
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TDA7333
RDS/RBDS PROCESSOR
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TDA7333January 2005
Features3rd ORDER HIGH RESOLUTION SIGMA
DELTA CONVERTER FOR MPX SAMPLING DIGITAL DECIMATION AND FILTERING
STAGES DEMODULATION OF EUROPEAN RADIO
DATA SYSTEM (RDS) DEMODULATION OF USA RADIO
BROADCAST DATA SYSTEM (RBDS) AUTOMATIC GROUP- AND BLOCK
SYNCHRONIZATION WITH FLYWHEEL
MECHANISM ERROR DETECTION AND CORRECTION PROGRAMMABLE INTERRUPT SOURCE
(RDS BLOCK,TA)I2 C/SPI BUS INTERFACE COMMON QUARTZ FREQUENCY 8.55 MHz
or 8.664MHz 3.3V POWER SUPPLY, 0.35 µm CMOS
TECHNOLOGY
DescriptionThe TDA7333 is a RDS/RDBS signal processor,
intended for recovering the inaudible RDS/RBDS
informations which are transmitted on most FM ra-
dio broadcasting stations.
RDS/RBDS PROCESSOR
Figure 2. Block DiagramRev. 1
TDA7333 Pin Connection
Figure 3. Pin Connection (Top view) PIN DESCRIPTION
Table 2. Pin Description
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TDA7333 Quick Reference
Table 3. Quick Reference (Tamb = 25°C, VDDA/VDDD = 3.3V, fosc = 8.55 MHz) Electrical Specifications
6.1 Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings
6.2 General Interface Electrical Characteristics
Table 5. General Interface Electrical Characteristics
TDA7333
6.3 Electrical CharacteristicsTamb = -40 to +85 °C, VDDA/VDDD = 3.0 to 3.6 V, fosc = 8.55 MHZ, unless otherwise specified
VDDD and VDDA must not differ more than 0.15 V
Table 6. Electrical Characteristics
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TDA7333 Functional Description
7.1 OverviewThe new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip. It recovers the
inaudible RDS/RBDS information which are transmitted on most FM radio broadcasting stations.
Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing
is done in the digital domain and therefore very economical. After filtering the highly oversampled output
of the A/D converter, the RDS/RBDS demodulator extracts the RDS DataClock , RDS Data Signal and
the Quality information. A next RDS/RBDS decoder will synchronize the bitwise RDS stream to a group
and block wise information. This processing includes an error detection and error correction algorithm. In
addition, an automatic flywheel control avoids exhaustive data exchange between the RDS/RBDS proces-
sor and the host.
The device operates in accordance with the EBU (European Broadcasting Union) specifications.
7.2 Sigma Delta ConverterThe Sigma Delta Modulator is a 3rd order (second order-first order cascade) structure. Therefore a multibit out-
put (2 bit streams) represents the analog input signal. A next digital noise canceller will take the 2 bit streams
and calculates a combined stream which is then fed to the decimation filter. The modulator works at a sampling
frequency of XTI/2. The oversampling factor in relation to the band of interest (57 kHz +- 2.4 kHz) is 38.
7.3 Sinc4/16 Decimation FilterThe oversampled data delivered from the modulator are decimated by a value of 16 with a 4th order Sinc Filter.
This is considered to be the optimum solution for high decimation factors and for a 3rd order sigma delta mod-
ulator.
Table 6. Electrical Characteristics (continued)
TDA7333 The architecture is a very economical implementation because digital multipliers are not required. It is imple-
mented by cascading 4 integrators operating at full sampling rate (XTI/2) followed by 4 differentiators operating
at the reduced sampling rate (XTI/2/16). Also wrap around logic is allowed and the internal overflow will not af-
fect the output signal as long as a minimum required bit width is maintained.
The transfer function of this Sinc4/16 filter is:
with K = 4, M = 16
and its frequency response is:
with
Figure 4. Transfer function of a 4th order Sinc Filter, decimation factor is 16.() 1----- 1z M––1––--------------------Kjω() 1--------------sin----sin
-----------------------K 2πf-----=
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TDA7333
Figure 5. Magnitude Response of Sinc4/16 Filter in RDS Band
7.4 RDS Bandpass Filter and InterpolatorThe 8th order digital RDS bandpass filter is of type Tschebyscheff and centered at 57 kHz. With linear phase
characteristics in the passband and approximately flat group delay it guarantees best filter function of the RDS
and ARI signal. Four biquads are cascaded working at a common sampling frequency of XTI/2/16.
Figure 6. Transfer Function of RDS Bandpass Filter
TDA7333
Figure 7. Phase Response of the RDS Bandpass FilterThe output sample of the bandpass filter is picked up from a linear interpolator with sinc2 characteristics. The
interpolation factor is 32. A zero cross detection is simply formed by taking the sign bit of the interpolated signal.
This signal which contains only phase informations is processed by the RDS Demodulator.
7.5 Demodulator The demodulator includes : RDS quality indicator with selectable sensitivity Selectable time constant of 57kHz PLL Selectable time constant of bit PLL time constant selection done automatically or by software
Figure 8. Demodulator Block Diagram
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TDA7333The demodulator is fed by the 57 KHz bandpass filter and interpolated multiplex signal. The input signal
passes a digital filter extracting the sinus and cosinus components, to be used for further processing.
The sign of both channels are used as input for the ARI indicator and for the 57 KHz PLL.
A fast ARI indicator determines the presence of an ARI carrier. If an ARI carrier is present, the 57 KHz
PLL is operating as a normal PLL, else it is operating as a Costas loop.
One part of the PLL is compensating the integral offset (frequency deviation between oscillator and input
signal).
One channel of the filter is fed into the half wave integrator. Two half waves are created, with a phase
deviation of 90 degrees. One wave represents the RDS component, whereas the other wave represents
the ARI component. The sign of both waves are used as reference for the bit PLL (1187.5 Hz).
The RDS wave is then fed into the half wave extractor. This leads into an RDS signal, which after integra-
tion and differential decoding represents the RDS data.
In a similar way a quality bit can be calculated. This is useful to optimize error correction.
The module needs a fixed clock of 8.55 MHz. Optionally an 8.664 Mhz clock may be used by setting the
corresponding bit in rds_bd_ctrl register (cf page 13).
In order to optimize the error correction in the group and block synchronization module, the sensitivity level
of the quality bit can be adjusted in three steps (cf page15). Only bits marked as bad by the quality bit are
allowed to be corrected in the group and block synchronization module. Thus the error correction is directly
influenced by this setup.
The time constant of the 57KHz PLL and the 1187.5Hz PLL may be influenced by software (cf page13).
This is useful in order to achieve a fast synchronization after a program resp. frequency change (fast time
constant) and to get a maximum of noise immunity after synchronization (slow time constant).
The user may choose between 2 possibilities via bit rds_bd_ctrl[1] (cf page13):
a: Hardware selected time constant - In this case both pll time constants are reset to the fastest one with
a reset from the group and block synchronization module. If the software decides to resynchronize, it
generates a reset . Both PLL are set to the fastest time constant, which is automatically increased to
the slowest one. This is done in four steps within a total time of 215.6ms (256 RDS clocks).
b: Software selected time constant - In this case the time constant of both PLL can be selected individually
by software.PLL time constants can be set independently.
TDA7333
7.6 Group and block synchronization moduleThe group and block synchronization module has the following features : Hardware group and block synchronization Hardware error detection Hardware error correction using the quality bit information of the demodulator Hardware synchronization flywheel TAinformation extraction reset by software (ar_res)
Figure 9. Group and block synchronization block diagramThis module is used to acquire group and block synchronization of the received RDS data stream, which is pro-
vided in a modified shortened cyclic code. For the theory and implementation of the modified shortened cyclic
code, please refer to the specification of the radio data system (RDS) EN50067.
It further detects errors in the data stream. Depending on the quality bit information of the demodulator an error
correction is made.
The RDS data bytes are available to the software together with status bits giving an indication on the reliability
of the data.
It also extracts TA information which can be used as interrupt source (cf page 12).
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TDA7333
7.7 Programming through Serial bus interfaceThe serial bus interface is used to access the different registers of the chip. It is able to handle both I2C and SPI
transfer protocols, the selection between the two modes is done thanks to the pin CSN : if the pin CSN is high, the interface operates as an I2C bus. if the pin CSN is asserted low, the interface operates as a SPI bus.
In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip.
Depending on the transfer mode, external pins have alternate functions as following:
Table 7. Eight registers are available with read or read/write access rights as following :
Table 8. The meaning of each bit is described below :
