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TDA7319STN/a12avai3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
TDA7319STMN/a35avai3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR


TDA7319 ,3 BAND DIGITAL CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb =25°C Re ..
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TDA7319
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
TDA7319
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
ONE STEREO INPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTION

The TDA7319 is a volume and tone (bass , mid-
dle and treble) processor for quality audio appli-
cation in car radio and Hi-Fi system.
Control is accomplished by serial I2 C bus micro-
processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/MOS Technology,
Low Distortion, Low Noise and Low Dc stepping
are obtained.
BLOCK DIAGRAM AND APPLICATION CIRCUIT
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
QUICK REFERENCE DATA
PIN CONNECTION
TDA7319
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb =
25°C Refer to the test circuit, unless otherwise specified.)
TDA7319
ELECTRICAL CHARACTERISTICS (continued)
Note 1: the device is functionally good at Vs = 5V. A step down, on VS, to 4V does’t reset the device.
APPLICATION SUGGESTIONS

The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute)
with a 1dB step.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7319 audioprocessor provides 3 bands
tones control.
Bass, Middle Stages

The Bass and the middle cells have the same
structure.
The Bass cell has an internal resistor Ri = 44KΩ
typical.
The Middle cell has an internal resistor Ri = 25KΩ
typical.
Several filter types can be implemented, connect-
ing external components to the Bass/Middle IN
and OUT pins.
The fig.1 refers to basic
starting from the filter component values (R1 in-
ternal and R2,C1,C2 external) the centre fre-
quency Fc, the gain Av at max. boost and the fil-
ter Q factor are computed as follows:
FC = 1
2 ⋅ π ⋅√  Ri, R2, C1, C2
AV = R2 C2 + R2 C1 + Ri C1
R2 C1 + R2 C2
Q = √ Ri R2 + C1 C2
R2 C1 + R2 C2
Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:
C1 = AV − 1
2 ⋅ π ⋅ Ri ⋅ Q C2 = Q2 ⋅ C1
AV − 1 Q2
R2 = AV − 1 − Q2
2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q
Treble Stage

The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
CREF

The suggested 10μF reference capacitor (CREF)
value can be reduced to 4.7μF if the application
requires faster power ON.
Figure 1.
TDA7319
Figure 2: Noise vs. volume setting Figure 3: SVRR vs. frequency
Figure 4: THD vs. frequency Figure 5: THD vs. RLOAD
Figure 6: Channel separation vs. frequency Figure 7: Output clip level vs. Supply voltage
TDA7319
Figure 8: Quiescent current vs. supply voltage Figure 9: Quiescent current vs. temperature
Figure 12: Treble response Figure 13: Typical tone response
Figure 10: Bass response Figure 11: Middle response
TDA7319
Timing Diagram of I2 CBUS
Data Validity on the I2 CBUS2 C BUS INTERFACE

Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity

As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions

As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format

Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge

The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio-
processor, the μP can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Acknowledge on the I2 CBUS
TDA7319
SDA, SCL I2 CBUS TIMING
All values referred to VIH min. and VIL max. levels
(*) Must be guaranteed by the I2 C BUS master.
Definition of timing on the I2 C-bus
TDA7319
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