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TDA5221INFIEONN/a100avaiASK/FSK Single Conversion Receiver


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TDA5221
ASK/FSK Single Conversion Receiver
Wireless Components
ASK/FSK Single Conversion Receiver
TDA 5221 Version 0.1
Target Specification October 2001
Edition 10.01
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München

© InfineonTechnologiesAG October 2001.
All Rights Reserved.
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Product Info
Product Info
General Description
The IC is a very low power consump-
tion single chip FSK/ASK Superhet-
erodyne Receiver (SHR) for the
frequency band 300 to 340 MHz. The
IC offers a high level of integration and
needs only a few external compo-
nents. The device contains a low noise
amplifier (LNA), a double balanced
mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a lim-
iter with RSSI generator, a PLL FSK
demodulator, a data filter, a data com-
parator (slicer) and a peak detector.
Additionally there is a power down fea-
ture to save battery life.
Features
-Low supply current (Is = 6.4 mA
typ. in FSK mode, Is = 5.6 mA typ.
in ASK mode)Supply voltage range 5V ±10%Power down mode with very low
supply current (50nA typ.)FSK and ASK demodulation capa-
bilityFully integrated VCO and PLL
SynthesiserASK sensitivity better than
-110 dBm over specified tempera-
ture range (- 40 to +105°C)Selectable frequency ranges 300-
320 MHz and 300-340 MHzLimiter with RSSI generation,
operating at 10.7MHzSelectable reference frequency2nd order low pass data filter with
external capacitorsData slicer with self-adjusting
thresholdFSK sensitivity better than
-102 dBm over specified tempera-
ture range (- 40 to +105°C)
Applications
-Keyless Entry SystemsRemote Control SystemsAlarm SystemsLow Bitrate Communication
Systems
Ordering Information

samples available
Table of ContentsTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iProduct Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.1Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.2Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.3Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.4Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
3.2Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.3Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4.1Low Noise Amplifier (LNA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4.2Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.3PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.4Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.5Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.6FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4.7Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4.8Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4.9Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4.10Bandgap Reference Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14.1Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .2
4.2Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4.3Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.4Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.5Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.6ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.6.1FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.6.2ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.7Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
5.1Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
5.1.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
5.1.3AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
5.1.4AC/DC Characteristics at TAMB = -40 to 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Product Description2.1Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.3Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Product Description
2.1Overview

The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for receive frequencies between 300 and 340 MHz. The IC
offers a high level of integration and needs only a few external components. The
device contains a low noise amplifier (LNA), a double balanced mixer, a fully
integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI gen-
erator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a
peak detector. Additionally there is a power down feature to save battery life.
2.2Application
Keyless Entry SystemsRemote Control SystemsAlarm SystemsLow Bitrate Communication Systems
2.3Features
Low supply current (Is = 6.4 mA typ.FSK mode, 5.6 mA typ. ASK mode)Supply voltage range 5V ±10%Power down mode with very low supply current (50nA typ.)FSK and ASK demodulation capabilityFully integrated VCO and PLL SynthesiserRF input sensitivity ASK -113dBm typ. at 25°C, better than -110dBm over
complete specified operating temperature range (-40 to +105°C)RF input sensitivity FSK -105dBm typ. at 25°C, better than -102dBm over
complete specified operating temperature range (-40 to +105°C)Receive frequency range between 310 and 340 MHzSelectable reference frequencyLimiter with RSSI generation, operating at 10.7MHz2nd order low pass data filter with external capacitorsData slicer with self-adjusting threshold
2.4
Functional Description3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.3Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.4Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
Functional Description
3.1Pin Configuration

Pin_Configuration_5221.wmf
Figure 3-1IC Pin Configuration
Functional Description
3.2Pin Definition and Function

In the subsequent table the internal circuits connected to the pins of the device
are shown. ESD-protection circuits are omitted to ease reading.
Functional Description
Functional Description
Functional Description
Functional Description
Functional Description
Functional Description
3.3Functional Block Diagram

Functional_diagram_5221.wmf
Figure 3-2Main Block Diagram
3.4Functional Blocks
3.4.1Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
Functional Description
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2Mixer

The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-
tage gain of approximately 21dB by utilising either high- or low-side injection of
the local oscillator signal. In case the mixer is interfaced only single-ended, the
unused mixer input has to be tied to ground via a capacitor. The mixer is fol-
lowed by a low pass filter with a corner frequency of 20MHz in order to suppress
RF signals to appear at the IF output (IFO pin). The IF output is internally con-
sisting of an emitter follower that has a source impedance of approximately
330Ω=to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter
without additional matching circuitry.
3.4.3PLL Synthesizer

The Phase Locked Loop synthesizer consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO
was designed to guarantee over production spread and the specified tempera-
ture range a receive frequency range between 300 and 340 MHz depending on
whether high- or low-side injection of the local oscillator is used. The oscillator
signal is fed both to the synthesiser divider chain and to a divider that is dividing
the signal by 2 before it is applied to the downconverting mixer. Local oscillator
high side injection has to be used for receive frequencies between approxi-
mately 300 and 320 MHz, low side injection for receive frequencies between
320 and 340MHz - see also Section 4.4..
3.4.4Crystal Oscillator

The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is explained in Section 4.4.
3.4.5Limiter

The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80dB that has a bandpass-characteristic centred around
10.7MHz. It has a typical input impedance of 330 Ω=to allow for easy interfacing
to a 10.7MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal
Strength Indicator (RSSI) generator which produces a DC voltage that is
Functional Description
directly proportional to the input signal level as can be seen in Figure 4-2. This
signal is used to demodulate ASK-modulated receive signals in the subsequent
baseband circuitry. The RSSI output is applied to the modulation format switch,
to the Peak Detector input and to the AGC circuitry.
In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state
as described in the next chapter.
3.4.6FSK Demodulator

To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear
phase detector as is the output of the 10.7 MHz center frequency VCO. The
demodulator gain is typically 140µV/kHz. The passive loop filter output that is
comprised fully on chip is fed to both the VCO and the modulation format switch
described in more detail below. This signal is representing the demodulated sig-
nal with low frequencies applied to the demodulator demodulated to logic ones
and high frequencies demodulated to logic zeroes. However this is only valid in
case the local oscillator is low-side injected to the mixer which is applicable to
receive frequencies above 330MHz (e.g. 345MHz). In case of receive frequen-
cies below 330MHz (e.g.315MHz) high frequencies are demodulated as logical
ones due to a sign inversion in the downconversion mixing process. See also
Section 4.4.
The modulation format switch is actually a switchable amplifier with an AC gain
of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table.
This gain was chosen to facilitate detection in the subsequent circuits. The DC
gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset
produced by the demodulator in case of large frequency offsets of the IF signal.
The resulting frequency characteristic and details on the principle of operation
of the switch are described in Section 4.6.
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7Data Filter

The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ=on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
Functional Description
3.4.8Data Slicer

The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of up to 100kBaud. The maximum achievable
data rate also depends on the IF Filter bandwidth and the local oscillator toler-
ance values. Both inputs are accessible. The output delivers a digital data sig-
nal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold
on pin 20 its generated by a RC-term. In ASK-mode alternatively a scaled value
of the voltage at the PDO-output (approx. 87%) can be used as the slicer-
threshold. The data slicer threshold generation alternatives are described in
more detail in Section 4.5.
3.4.9Peak Detector

The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. A capacitor is necessary. The input is con-
nected to the output of the RSSI-output of the Limiter, the output is connected
to the PDO pin (Pin 26). This output can be used as an indicator for the received
signal strength to use in wake-up circuits and as a reference for the data slicer
in ASK mode. Note that the RSSI level is also output in case of FSK mode.
3.4.10Bandgap Reference Circuitry

A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Applications4.1Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . .4-2
4.2Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.4Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
4.5Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
4.6ASK/FSK Datapatch Functional Description. . . . . . . . . . . . . . . . . . . .4-8
4.7Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
Applications
4.1Choice of LNA Threshold Voltage and Time Constant

In the following figure the internal circuitry of the LNA automatic gain control is
shown.
LNA_autom.wmf
Figure 4-1LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimped-
ance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the
internal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control volt-
age.
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