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TCD2554DTOSN/a1370avaiCCD LINEAR IMAGE SENSOR
TCD2554DTOSHIBAN/a688avaiCCD LINEAR IMAGE SENSOR


TCD2554D ,CCD LINEAR IMAGE SENSORFEATURES0 Number of Image Sensing Elements: 5348 elementsx3 line0 Image Sensing Element Size : 8,um ..
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TCD2554D
CCD LINEAR IMAGE SENSOR
TOSHIBA TCD2554D
TOSHIBA CCD LINEAR IMAGE SENSOR CCD (Charge Coupled Device)
TCD2554D
The TCD2554D is a high sensitive and low dark current
5348 elementsx3 line CCD color image sensor which
includes CCD drive circuit, clamp circuit and sample and
hold circuit.
The sensor is designed for scanner. The device contains a
row of 5348 elementsx3 line photodiodes which provide
a 24 lines/mm (600DPI) across a A4 size paper. The device
is operated by 5V pulse, and 12V power supply.
FEATURES
0 Number of Image Sensing Elements
: 5348 elementsx3 line
0 Image Sensing Element Size : 8pm by 8pm on 8pm centers
It Photo Sensing Region : High sensitive and low dark . WDIP24-G-400-2.54A(B)
current PN photodiode Weight : 5.0g (Typ.)
0 Distance Between Photodiode Array : 32pm (4 Lines)
0 Clock : 2 phase (5V)
ct Power Supply : 12V Power supply voltage PIN CONNECTION
It Internal Circuit : Sample and Hold circuit, Clamp circuit V
0 Package : 24 pin CERDIP package OSI 1 F F v E OD
It Color Filter : Red, Green, Blue OS? 2 E SS
MAXIMUM RATINGS (Note 1) 053 3 E RS
SS 4 El sb1B
CHARACTERISTIC SYMBOL RATING UNIT -
SP 5 Elsm
Clock Pulse Voltage V¢A V cF 6 m o m EI‘FSW
Shift Pulse Voltage VSH V SS E m
Reset Pulse Voltage VR_S -0.3--8 V 7 18 ,
Clamp Pulse Voltage Va: V SS 8 ESHZ
Sample and Hold Pulse Voltage V? V SS 9 E ff1A2
Power Supply Voltage OD -0.3--15 V 10 w m m Esl 752”
VDD ¢2A3 11 vi',: rr'':',, il, EVDD
Operating Temperature Top, 0--60 C ff1A3 IE E SS
Storage Temperature Tstg -25--85 ''C
(Note 1) All voltage are with respect to SS terminals (Ground). (TOP VIEW) 980910EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to the foreign exchange and foreign trade laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert or other rights of the third
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1999-01-12 1/15
TOSHIBA
CIRCUIT DIAGRAM
PHOTO DIODE (B)
SHIFT GATE 1
CCD ANALOG SHIFT REGISTER (B)
PHOTO DIODE (G)
SHIFT GATE 2
CCD ANALOG SHIFT REGISTER (G)
PHOTO DIODE (R)
SHIFT GATE 3
CCD ANALOG SHIFT REGISTER (R)
TCD2554D
1 ¢1A3
11 ¢2A3
SS SP CP SS SS
PIN NAMES
PIN No. SYMBOL NAME PIN No. SYMBOL NAME
1 OSI Signal Output 1 (Blue) 13 SS Ground
2 OS2 Signal Output 2 (Green) 14 VDD Power (Digital)
3 053 Signal Output 3 (Red) 15 ¢2A2 Clock 2 (Phase 2)
4 SS Ground 16 ¢1A2 Clock 2 (Phase 1)
5 7 Sample and Hold Gate 17 SH2 Shift Gate 2
6 W Clamp Gate 18 ¢2A1 Clock 1 (Phase 2)
7 SS Ground 19 ¢1A1 Clock 1 (Phase 1)
8 SS Ground 20 SH1 Shift Gate 1
9 ss Ground 21 951B Final Stage Clock (Phase 1)
10 SH3 Shift Gate 3 22 AS" Reset Gate
11 fb2A3 Clock 3 (Phase 2) 23 SS Ground
12 ¢1A3 Clock 3 (Phase 1) 24 OD Power (Analog)
1999-01-12 2/15
TOSHIBA TCD2554D
OPTICAL/ ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VOD = VDD =12V, l/ff = VR-s = VSH --vc7 = 5V (PULSE), fp =1MHZ, Ws =1MHZ,
LOAD RESISTANCE =100k0, tINT (INTEGRATION TIME)=10ms,
LIGHT SOURCE = A LIGHT SOURCE + CMSOOS FILTER (t =1mm))
CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT NOTE
RR 9.0 12.9 16.8
Sensitivity RG 9.9 14.1 18.3 V/(Ix-s) (Note 2)
RB 3.5 5.0 6.5
Photo Response Non Uniformity PRNU (1) - 10 20 % (Note 3)
PRNU (3) - 3 12 mV (Note 4)
Image Lag IL - 1 - % (Note 5)
Saturation Output Voltage VSAT 2.75 - - V (Note 6)
Saturation Exposure SE - - - Ix-s (Note 7)
Dark Signal Voltage VDRK - 3.0 9 mV (Note 8)
Dark Signal Non Uniformity DSNU - 4.0 12 mV (Note 8)
DC Power Dissipation PD - 200 300 mW
Total Transfer Efficiency TTE 92 - - %
Output Impedance 20 - - 1.0 kfl
DC Signal Output Voltage Vos 3.0 5.0 7.0 V (Note 9)
Random Noise NDa - 0.9 - mV (Note 10)
Reset Noise VRSN - 200 - mV (Note 9)
(Note 2) Sensitivity is defined for each color of signal outputs average when the
photosensitive surface is applied with the light of uniform illumination and
uniform color temperature.
(Note 3) PRNU (1) is defined for each color on a single chip by the expressions below when
the photosensitive surface is applied with the light of uniform illumination and
uniform color temperature.
PRNU (1)=
% x100 (%)
WhenT is average of total signal output and AX is the maximum deviation from Y.
The amount of incident light is shown below.
Red=1/2-SE
Green=1/2-SE
Bule=1/4.SE
(Note 4) PRNU (3) is defined as maximum voltage with next pixel, where measured 5% of
SE (Typ.).
1999-01-12 3/15
TOSHIBA TCD2554D
(Note 5) Image Lag is defined as follows.
SHn n n n
LED -lo-NI OFF
os Image Lag
Signal
(500mV)
(Note 6) VSAT is defined as minimum saturation output of all effective pixels.
(Note 7) Definition of SE
sc-us-AT (Ixs)
(Note 8) VDRK is defined as average dark signal voltage of all effective pixels.
DSNU is defined as different voltage between VDRK and VMDK when VMDK is
maximum dark signal voltage.
"a VDRK
VMDK -
(Note 9) DC signal output voltage and Reset Noise is defined as follows, but Reset Noise is
a fixed pattern noise.
1999-01-12 4/15
TOSHIBA TCD2554D
(Note 10) Random noise is defined as the standard deviation (sigma) of the output level
difference between two adjacent effective pixels under no illumination (i.e. dark
conditions) calculated by the following procedure.
VIDEO OUTPUT VIDEO OUTPUT
OUTPUT WAVE FORM
(EFFECTIVE PIXELS 200ns 200ns
UNDER DARK CONDITION) - -.--.-.-_---- F - F __________ L
PIXEL (n) PIXEL (n + 1)
1) Two adjacent pixels (pixel n and n+1) in one reading are fixed as measurement
points.
2) Each of the output level at video output periods averaged over 200ns period to
get V(n) and V(n+1).
3) V(n + 1) is subtracted from V(n) to get AV.
AV=V(n)-V(n+1)
4) The standard deviation of AV is calculated after procedure 2) and 3) are
repeated 30 times (30 readings).
1 30 1 30 . _2
V---' . a: - 2 (AVI -nv)
r'0islz11/il V 30i=1I I
5) Procedure 2), 3) and 4) are repeated 10 times to get sigma value.
6) 1O sigma values are averaged.
- 1 10 .
a - 10 j =21 J)
7) Fualue calculated using the above procedure is observed sritimes larger than
that measured relative to the ground level. So we specify random noise as
follows.
1999-01-12 5/15
TOSHIBA TCD2554D
OPERATING CONDITION
CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT NOTE
k "H" Level 4.75 5.0 5.5
Cloc Pulse Voltage "L" Level V/A 0.0 0.0 0.3 V
. "H" Level 4.5 5.0 5.5
Shift Pulse Voltage "L" Level VSH 0.0 0.0 0.3 V (Note 11)
"H" Level - 4.5 5.0 5.5
Reset Pulse Voltage "L'' Level VRS 0.0 0.0 0.3 V
Sam Ie and Hold Pulse "H" Level - 4.5 5.0 5.5
Voltzge "L'' Level VSP 0.0 0.0 0.3 V (Note 12)
Clamp Pulse Voltage "H" Level vep 4.5 5.0 5.5 V
"L" Level 0.0 0.0 0.3
Power Supply Voltage (Analog) VOD 11.4 12.0 13.0 V
Power Supply Voltage (Digital) VDD 11.4 12.0 13.0 V
(Note 11) IHA''"'' means the high level voltage of V¢A when SH pulse is high level.
(Note 12) Supply "L" Level to 3-5 terminal when sample and hold circuitry is not used.
CLOCK CHARACTERISTICS (Ta = 25°C)
CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT
Clock Pulse Frequency f/A 0.3 1.0 5.0 MHz
Reset Pulse Frequency m-s 0.3 1.0 5.0 MHz
Clamp Pulse Frequency fc7 0.3 1.0 5.0 MHz
Sample and Hold Pulse Frequency fsT 0.3 1.0 5.0 MHz
Clock Capacitance Css/s - 400 550 pF
Final Stage Clock Capacitance Cgis - 15 30 pF
Shift Gate Capacitance CSH - 20 30 pF
Reset Gate Capacitance CR_S - 20 30 pF
Sample and Hold Gate Capacitance CS_p - 20 30 pF
Clamp Gate Capacitance CE) - 20 30 pF
1999-01-12 6/15
TCD2554D
TOSHIBA
L—GVSSZGDJ.
(SLNEWE‘IH 6825) 0018321 anGVEH 3N” l.
(smawau 6) (SiNawa‘Ia 91755) (SiNawa‘Ia ZS) smdmo AWWflO
(1N3W313 1) smamo Awwna smamo ‘IVNDIS
indino AWWflG_\
// (51N3wa13 v) \ / (smawau 9:) (SlN3W313 EL)
{1N3w313 L) smuno \( / Sifldmo smamo AWWF‘ICI
smawana E)
Slndan 1531/ AWWnG 013le .LHDI‘I
(smuno H / s)
_JUULfl_fl_flJLLflJU1;JUUUUUUL;JUUUUUUUULgJUUUUUUUngUULfl___JLfl_ 22
WWWWM &
mmmmmmmmmmmr—uv m.
___nnnnnnnnnnflnHHHHnfinnnnnnnnflnnnnnnnflnnnn nngmo
(l H {I (l
I J) )J I I
)l )J H5
(awu Nouvassml) 1le
(300w dWV‘D us)
1mm) 9mm;
1999-01-12 7/15
TCD2554D
TOSHIBA
8~GVSSZCDl
(SiNEIWaE GEES) OOIHBd anCIVSH 3Nl'l I.
(smawau 6) (smawau svss) (smawan zr.) smamo Awwna
UN3W313 l) smuno Awwna smdmo 1VND|S
Lndmo Awwno‘\
// (SlNiWE'IE! p) \ / (SlN3W313 91) (SLNBWB‘H El.)
(mawau l.) 51nd1no \(51N3w313 9/ smdmo smamo AWWHG
smamo 1531/ Awwnc] mains man
(smamo H / S)
mmmmmmmmmmuu—Ur m
WWWWWW‘LMH n n n m
[L 41L (9 4(
..___l u n I I HS
(awn; Nouvasaml) 1le
(300w dWV‘D aNn)
1mm: emwu
1999-01-12 8/15
TOSHIBA
TIMING REQUIREMENTS
(LINE CLAMP MODE)
(LINE CLAMP MODE)
TCD2554D
3.5V (MAX.)
1.5V (MIN.)
ffi? I
t9 t10 tll
t13 t14
_ t12 t15 t16
t28 t17
OS i 3/ Reference level 's, Video signal
t23 t22 [
- t19 t20
8 , t24
- t21 t25 t26
Sp' 8 il
1999-01-12 9/15
TOSHIBA TCD2554D
TIMING REQUIREMENTS (Cont.)
CHARACTERISTIC SYMBOL MIN. (Ngep'm MAX. UNIT
. . t1 120 1000 -
Pulse Timing of SH and fbl t5 800 1000 - ns
SH Pulse Rise Time, Fall Time t2, t4 0 50 - ns
SH Pulse Width t3 3000 5000 - ns
Pulse Timing of SH and E13 t6 0 500 - ns
951, 952 Pulse Rise Time, Fall Time t7, t8 0 50 - ns
Pulse Timing of fSA and Cs t9 100 - - ns
TIS' Pulse Rise Time, Fall Time t10, t11 0 20 - ns
FG Pulse Width t12 30 100 - ns
Pulse Timing of E and W t13 150 200 - ns
Pulse Timing of ¢1A, /2A and tTi t14 10 50 - ns
W Pulse Rise Time, Fall Time t15, t16 0 20 - ns
3 Pulse Width t17 40 100 - ns
Video Data Delay Time (Note 14) t18 - 80 - ns
- . . . t19, t20,
SP Pulse Rise Time, Fall Time t25, t26 0 20 - ns
s7 Pulse Width t21, t27 40 100 - ns
Pulse Timing of E and s7 t22 0 20 - ns
Pulse Timing of §T3 and ¢1B t23, t24 0 10 - ns
Pulse Timing of AT and RS-noise t28 - (Note 15) - gs
(Note 13) TYP. is the case of fR-s--1.0MHz
(Note 14) Load resistance is 100kQ
1999-01-12 10/15
TOSHIBA
TCD2554D
(Note 15)
t28 (ns)
0 100 200 300 400
RS PULSE WIDTH (ns)
APPLICATION NOTE
Mode Select
ON OFF
Sample and Hold s7 Pulse S7=Low
Bit Clamp Line Clamp
Clamp Mode 5 Pulse W=W
1999-01-12 11/15
TOSHIBA
TCD2554D
TYPICAL SPECTRAL RESPONSE/MODULATION TRANSFER FUNCTION
RELATIVE RESPONSE
MODULATION TRANSFER FUNCTION
OF X-DIRECTION
SPATIAL FREQUENCY (Cycles/mm)
SPECTRAL RESPONSE
Ta = 25°C
450 500 550 600 650 700
WAVE LENGTH l (nm)
MODULATION TRANSFER FUNCTION
OF Y-DIRECTION
SPATIAL FREQUENCY (Cycles/mm)
0 12.5 25 37.5 50 62.5 0 12.5 25 37.5 50 62.5
1.0 '_....
A=550nm A=550nm "ss,
'ss,, 's,
0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0
NORMALIZED SPATIAL FREQUENCY
NORMALIZED SPATIAL FREQUENCY
1999-01-12 12/15
TOSHIBA TCD2554D
TYPICAL DRIVE CIRCUIT
0.1 F/25V +5V
l. +5V
0.1;zF/25V
10pF/25V 0.1,uF/25V
-a', J, '1
I'__ -n
", ¢2A1 I I r-------,
545 l i 'e,
L--.--., I I
J, IC3 l l
s61Al,t I V
I OQ l "N
sS1A2,r {
I o< l
sb2Ait,t I
l otC] i
12V ¢1A3! l
+ . <1 5
ss2A3I os:0 l
0.1/AF/25V l l
-"- 9513 l ot0 I
10prF/25V l -,l
-te, 2 IO
WHEN zamrzlmrzlns‘lrrnja
OD SS _s ss1Bsm1ss1Al ff2A1 SH2 ¢1A2 ¢2A2 VDD
. TCD2554D
OSI 052 0§3 SS s-p c-p SH3 'ii-iii-iii:.,., ¢1A3
1 2 3 4 5
uuu Lis'-'"'''-"-')-"')-"')'-"'?''')-').;)---.-.- IWW
M c-- ---,
SH1 I I
" d " l o<} I Y,,
R14 R11: R1::12v 5H2: l
I l o<} l x
. 0.1/15/25v SH3 l cl l l
. l 10ptF/25V 5: l
R1 R1::R1 p, : ot:0i!-_
l I + - I I
TR1/I ro SP l :l I :
Oslo- I I
TR1 E l ] l
TRI)i-
R215 R215 mi
ICI, 2, 3 : TC74HC04AP
TR1 : 2SC1815-Y
R1 : 1500
R2 : 150051
1999-01-12 13/15
TOSHIBA TCD2554D
CAUTION
l. Window Glass
The dust and stain on the glass window of the package degrade optical performance of CCD
sensor.
Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface,
and allow the glass to dry, by blowing with filtered dry N2.
Care should be taken to avoid mechanical or thermal shock because the glass window is easily to
damage.
2. Electrostatic Breakdown
Store in shorting clip or in conductive foam to avoid electrostatic breakdown.
3. Incident Light
CCD sensor is sensitive to infrared light.
Note that infrared light component degrades resolution and PRNU of CCD sensor.
4. Lead Frame Forming
Since this package is not strong against mechanical stress, you should not reform the lead frame.
We recommend to use a IC-inserter when you assemble to PCB.
1999-01-12 14/15
TOSHIBA TCD2554D
OUTLINE DRAWING
WDIPZ4-G-400-2.54A(B) Unit : mm
(Note 1) (Note 3)
5.9i0.8 42.8(8sunx5348) 0710.1
0.5R r "1”? ,lf
K Ln , CD
l CD ei
'fd. 8
m1? ci "
(Note 4) 1 _ " I(Note 2)
6.9i0.8 _,1 ne 0.3
" 53.6i0.5 CC.)
T "] SE:
I I l 0)
I l Ix.
-Ci- I
-s,r'-
2.54 0.8 0.5 31"
(Note I) No.1 SENSOR ELEMENT (SI) TO EDGE OF PACKAGE.
(Note 2) TOP OF CHIP TO BOTTOM OF PACKAGE.
(Note 3) GLASS THICKNESS (n = 1.5)
(Note 4) No.1 SENSOR ELEMENT (SI) TO EDGE OF No.1 PIN.
Weight : 5.0g (Typ.)
1999-01-12 15/15

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